Random Bit Stream Circuit Using Jitter-Synchronized Sampling
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Solution Overview
Problem
Existing random number generators face challenges in producing high-quality random bit streams due to issues like offset voltage, bandwidth limitations, and synchronization with system clocks, which affect the unpredictability and statistical quality of the output, especially in integrated chip-card implementations.
Innovation Solution
A digital apparatus that synchronizes the sampling edge of the sample signal with the clock signal using a delay line and feedback loop, allowing for the generation of high-quality random bit streams even with low jitter levels, and compensates for system clock disturbances, implemented using digital gates for ease of integration and portability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If jittered oscillator sampling is used to generate random bit streams, then the unpredictability of the output is improved, but the synchronization with system clock becomes problematic due to periodic disturbances reducing oscillator jitter
Solution Approach 1:
The patent employs a feedback mechanism where the system monitors the random bit stream output and adjusts the sampling timing accordingly. The feedback loop detects periodic disturbances caused by system clock synchronization and dynamically modifies the sampling instant to maximize jitter utilization, thereby maintaining unpredictability while operating in a synchronized environment.
Solution Approach 2:
The invention introduces dynamic adjustment of sampling parameters based on real-time conditions. The sampling frequency and timing are made variable rather than fixed, allowing the system to adapt to periodic disturbances from the system clock. This dynamic behavior enables the oscillator to maintain its jitter characteristics despite synchronization requirements.
2Device complexity
If direct amplification of noise source is used, then the random bit stream generation is simplified, but offset voltage and bandwidth limitations reduce the quality of the output
Solution Approach 1:
The patent replaces the analog amplification-based noise source with a digital oscillator-based approach. Instead of amplifying physical noise signals through analog circuits (which suffer from offset voltage and bandwidth limitations), the invention uses digital oscillators whose jitter characteristics provide the randomness. This substitution eliminates the harmful analog effects while maintaining or improving random bit stream quality.
Solution Approach 2:
The invention changes the fundamental parameter used for random bit generation from noise amplitude (in analog systems) to oscillator timing jitter (in digital systems). By shifting from amplitude-based randomness to time-based randomness, the system avoids offset voltage issues and bandwidth limitations while achieving high-quality random output through parameter transformation.
3Measurement precision
If sampling frequency is increased to improve random bit stream quality, then the statistical quality is improved, but the bandwidth requirements and device complexity increase
Solution Approach 1:
The patent transitions from increasing sampling frequency (time domain approach) to utilizing oscillator jitter characteristics (frequency/phase domain approach). Instead of sampling faster to capture more randomness, the invention extracts randomness from the inherent timing variations of oscillators operating at their natural frequencies. This dimensional shift from time-based to frequency-based randomness extraction avoids the bandwidth and complexity penalties of high-speed sampling.
Data Source
AI summary
An apparatus for providing a random bit stream includings a first provider for providing a clock signal, a second provider for providing a sample signal, an activator for activating the first and second providers such that a sampling edge of the sample signal is aligned to an edge of the clock signal. The apparatus further includes a sampler for sampling the clock signal responsive to the sampling edge of the sample signal and for generating a random bit dependent on the sampled state of the clock signal. Further, the apparatus includes a deactivator for deactivating the first and second providers. Successive random bits form a random bit stream.