Random Cache Line Selection for Virtualization Memory Duplication

The patent divides a memory page into multiple cache line-sized segments. Instead of comparing entire memory pages (typically 4KB), the system compares individual cache lines (typically 64 bytes). This segmentation reduces the comparison data size by a factor of 64, allowing faster identification of identical memory pages while maintaining accuracy through subsequent full-page verification only when cache line matches are found.

The patent implements partial comparison by examining only a subset of memory page contents (specific cache lines) rather than performing complete memory page comparisons. This partial action serves as a filtering mechanism: if cache lines don't match, the entire page comparison is avoided. Only when cache line matches are found does the system perform the excessive action of full page verification to ensure accuracy.

The patent segments the memory comparison task into two stages: first comparing individual cache lines (64 bytes each) and then performing full page comparison only when cache lines match. This segmentation reduces CPU processing power consumption by avoiding unnecessary full-page comparisons for non-identical memory pages, while maintaining duplication reliability through the two-stage verification process.

The system performs partial comparison (cache line level) as a preliminary filter before committing to full page comparison. This partial action significantly reduces CPU processing power requirements by eliminating most comparison operations early, while the excessive action (full page comparison) is performed only when necessary to ensure duplication reliability.