Random Circuit Layer Block Test Chip Generation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The verification of modern circuit designs and manufacturing processes becomes increasingly challenging due to their complexity and the decreasing physical sizes of transistors, leading to difficulties in testing and validating new technology nodes without viable test chips.
Innovation Solution
The development of a realistic test circuit generation technology that uses random circuit layer blocks to create test circuits through a bottom-up approach, mimicking actual IC designs and stressing specific design rules, thereby enabling more effective testing of manufacturing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional top-down test chip generation techniques are used, then test chips can be generated quickly, but the generated test chips fail to reflect characteristics of actual chip designs and have limited effectiveness in stressing manufacturing process constraints
Solution Approach 1:
The patent segments the test chip generation process into hierarchical levels: standard cell generation, circuit layer block generation, and full test chip assembly. Each level generates components that are then combined to form higher-level structures, enabling realistic test chip generation while maintaining efficiency through modular construction
Solution Approach 2:
The patent inverts the conventional top-down approach by implementing a bottom-up generation methodology. Instead of generating entire test chips from scratch, it builds upward from standard cells to circuit layer blocks to complete test chips, ensuring that each component adheres to design rules and realistic characteristics before integration
2Productivity
If purely random chip generation is used, then large numbers of test patterns can be produced efficiently, but the generated chips lack fundamental IC design process considerations and fail to mimic actual IC products
Solution Approach 1:
The patent applies parameter changes by controlling random generation processes with design rule constraints and quality metrics. Generation parameters such as cell dimensions, spacing, and layout patterns are adjusted to match actual IC design characteristics while maintaining generation efficiency
Solution Approach 2:
The patent copies realistic design characteristics from actual IC products into the generation process. By analyzing and replicating fundamental IC design process considerations, patterns, and attributes, the system generates test chips that mimic real products rather than purely random structures
3Ease of manufacture
If test chips are generated without considering fundamental IC design processes, then generation is simpler and faster, but verification of manufacturing processes becomes less effective
Solution Approach 1:
The patent performs preliminary actions by pre-generating and validating standard cells and circuit layer blocks before assembling complete test chips. Each component is generated with embedded design rule compliance and quality checks, ensuring that manufacturing verification effectiveness is built into the generation process itself rather than added later
Data Source
AI summary
A method may support realistic test circuit generation through random circuit layer blocks. The method may include accessing a set of circuit layer blocks, performing a block-level design rule check (DRC) process on the set of circuit layer blocks, wherein the block-level DRC process applies selected design rules that are a subset of a design rule set for a circuit manufacturing process, and obtaining a set of clean circuit layer blocks by discarding circuit layer blocks in the accessed set of circuit layer blocks that fail the block-level DRC process and keeping circuit layer blocks in the accessed set of circuit layer blocks that pass the block-level DRC process. The method may also include generating a test circuit layer formed through randomly selected circuit blocks from the set of clean circuit layer blocks and utilizing the test circuit layer in support of testing the circuit manufacturing process.