Random Clock Divider Pattern for RF Spur Mitigation
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Solution Overview
Problem
Multi-radio systems-on-chip (SoCs) face interference issues due to digital circuits generating harmonics that fall within the frequency band of RF circuits, causing performance degradation in RF operations, as digital clock signal harmonics can act as spurs and interfere with RF signals, making it challenging to choose a digital clock frequency that avoids interference.
Innovation Solution
A signal interference mitigation circuit is introduced, comprising a clock divider circuit and a control circuit that generates a first clock signal based on a second clock signal and a division factor pattern, where the division factors are randomly selected to control the throughput frequency, thereby mitigating interference by spreading energy across frequencies and suppressing harmonics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If digital circuits operate at a fixed clock frequency, then the digital circuits can function efficiently with stable timing, but harmonics of the clock signal may fall within the frequency band of RF circuits causing interference
Solution Approach 1:
The patent applies dynamics by making the clock frequency variable rather than fixed. The digital circuit clock frequency is dynamically adjusted based on the operational state of RF circuits. When RF circuits are active, the digital clock frequency is modified to avoid generating harmonics that would interfere with RF frequency bands. This dynamic adjustment resolves the contradiction by allowing efficient digital operation while preventing harmful interference through adaptive frequency selection.
2Object-affected harmful factors
If the digital clock frequency is changed to avoid interfering with RF circuits, then interference is reduced, but the digital circuit performance may be impacted
Solution Approach 1:
The patent employs parameter changes by systematically varying the digital clock frequency parameter to eliminate harmful harmonics. The system identifies frequency bands used by RF circuits and adjusts the digital clock frequency accordingly to ensure that no harmonic of the clock signal falls within these protected bands. This parameter adjustment reduces interference while maintaining digital circuit performance through controlled frequency modification rather than arbitrary changes.
3Area of stationary object
If multiple RF circuits and digital circuits coexist on the same silicon die, then integration density is improved, but signal interference between circuits increases
Solution Approach 1:
The patent applies segmentation by dividing the frequency spectrum into protected bands (used by RF circuits) and available bands (for digital circuits). The system segments the operating frequencies to ensure that digital circuit harmonics do not overlap with RF circuit frequency bands. This frequency segmentation allows multiple RF and digital circuits to coexist on the same silicon die with minimal interference, thereby maintaining high integration density while reducing harmful interactions.
Data Source
AI summary
Several methods and circuits configured to mitigate signal interference of at least one aggressor circuit operable on a first clock signal within an interfering frequency range of at least one victim circuit in an IC are disclosed. In an embodiment, a signal interference mitigation circuit is configured to be associated with the aggressor circuit and includes a clock divider circuit and a control circuit. The clock divider circuit is configured to generate the first clock signal based on a second clock signal and a division factor pattern. The control circuit is coupled with the clock divider circuit and configured to determine the division factor pattern and provide the division factor pattern to the clock divider circuit. The division factor pattern comprises a plurality of division factors selected randomly based on a plurality of random numbers, and is configured to control a throughput frequency associated with the signal interference mitigation circuit.