Random Clock Circuit Using Frequency Switching for Low-Jitter ADC Sampling
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Solution Overview
Problem
High-speed analog-to-digital converters in 5G millimeter wave and broadband communication systems face challenges in achieving low jitter and randomization of sampling clocks, which is essential for minimizing spurious signals and improving linearity.
Innovation Solution
A low-jitter random clock generation circuit is designed with a modular structure comprising a clock division and pulse generation module, a pseudorandom number generation module, a status control module, and a random clock output module. This circuit performs frequency division processing, generates pseudorandom numbers, and uses status control signals to randomly sample frequency division clocks, thereby producing low-jitter random clocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a high-speed sampling clock is used in ADC, then the sampling rate increases to meet 5G bandwidth requirements, but the jitter increases which degrades the spurious-free dynamic range and linearity
Solution Approach 1:
The patent applies dynamics by making the sampling clock frequency variable rather than fixed. The clock signal randomly switches between different frequency values (f1, f2, ..., fN) according to a probability distribution, allowing the system to adapt dynamically to minimize spurious components while maintaining high sampling rates. This dynamic frequency adjustment resolves the contradiction by enabling high-speed operation without the performance degradation caused by fixed-frequency jitter.
Solution Approach 2:
The patent changes the frequency parameter of the sampling clock from a single fixed value to multiple variable values. By introducing a spectrum of frequency components and randomly selecting among them, the system transforms the deterministic clock signal into a stochastic one. This parameter change allows the ADC to achieve high sampling rates while the randomization converts coherent spurious signals into distributed noise, thereby improving the spurious-free dynamic range.
2Device complexity
If a fixed frequency sampling clock is used, then the clock generation is simple, but spurious signals appear at specific frequencies which degrades the spurious-free dynamic range
Solution Approach 1:
The patent converts the harmful effect of coherent spurious signals into beneficial distributed noise. By introducing random frequency variations in the sampling clock, the deterministic spurious components that would normally appear at specific frequencies are transformed into random noise spread across the frequency spectrum. This randomization technique converts the harm of complex clock generation into the benefit of improved spurious-free dynamic range, as the noise can be more easily filtered or averaged out.
Solution Approach 2:
The patent introduces dynamic frequency switching to eliminate fixed-frequency spurious signals. The sampling clock randomly selects from multiple frequency values, preventing the formation of coherent spurious components at any single frequency. This dynamic approach trades the simplicity of a fixed-frequency clock for the benefit of significantly reduced spurious signals, improving the overall signal quality and dynamic range of the ADC system.
3Reliability
If random frequency switching is implemented in the sampling clock, then spurious components are converted to white noise improving dynamic range, but the clock generation circuit complexity increases
Solution Approach 1:
The patent segments the clock generation function into multiple independent components: a base clock source, a frequency division module that creates multiple frequency variants, a random selection module that chooses among them, and a synthesis module that combines them. This segmentation allows each component to be optimized independently and simplifies the overall design by breaking down the complex random frequency generation into manageable modular stages, thereby reducing the practical implementation complexity while maintaining the spurious-free dynamic range benefits.
Data Source
AI summary
A low-jitter random clock generation circuit includes: a clock division and pulse generation module connected to an input clock, performing frequency division processing to obtain frequency division clocks, and then detecting some frequency division clocks one by one to obtain frequency division pulses in a one-to-one correspondence; a pseudorandom number generation module connected to one frequency division clock, and generating a pseudorandom number; a status control module connected to all the frequency division clocks and the pseudorandom number to generate status control signals; and a random clock output module connected to the input clock, all the frequency division clocks, all the frequency division pulses, and all the status control signals, randomly sampling the frequency division clocks by using the frequency division pulses under control of the status control signals, and synchronously outputting the randomly sampled frequency division clocks by using the input clock, to obtain random clocks.