Random Clock Pulse Reduction for Secure Processing Speed
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current clock signal generators, whether pseudo-random or purely random, fail to provide an ideal solution for securing clock signals in secure elements, as pseudo-random generators are predictable and purely random generators can be too slow for practical use.
Innovation Solution
A random clock generator that receives a master clock signal and adjusts its frequency by varying the number of pulses using a clock signal reduction circuit and a number generator, which introduces randomness in the pulse frequency, ensuring unpredictability while maintaining a controllable processing speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a pseudo-random generator is used to mask the clock signal, then the clock signal can be partially masked, but the generator remains repetitive and predictable after a certain time
Solution Approach 1:
The patent applies dynamics by making the clock signal parameters variable rather than fixed. The period M and number of pulses N are dynamically changed according to a random sequence, transforming the static pseudo-random approach into a dynamic system where the clock characteristics continuously adapt, ensuring unpredictability while maintaining controllable average speed.
Solution Approach 2:
The patent changes the parameters of the clock signal (period M and number of pulses N) according to a random sequence. By varying these parameters dynamically, the system achieves unpredictability without completely sacrificing processing speed, as the average values can be controlled while introducing random variations that prevent prediction.
2Reliability
If a purely random clock generator is used, then the clock signal becomes unpredictable, but the clock frequency becomes much too slow for the required use
Solution Approach 1:
The patent applies partial action by selectively passing N pulses out of M clock cycles through a random mechanism. Instead of completely randomizing the clock (which would be too slow), it partially passes pulses based on a random ratio N/M, achieving unpredictability while maintaining a controllable average frequency that is sufficient for practical use.
Solution Approach 2:
The patent changes the parameters M (period) and N (number of pulses) according to a random sequence, allowing the clock frequency to vary dynamically. This enables the system to maintain an acceptable average speed while introducing random variations that prevent prediction, resolving the contradiction between speed and unpredictability.
3Reliability
If the number of pulses N is varied randomly every P clock cycles, then the clock signal becomes unpredictable and secure, but the device complexity increases
Solution Approach 1:
The patent segments the clock signal generation into distinct functional blocks: a random number generator that produces the sequence, a control unit that manages the timing (every P cycles), and a pulse selection mechanism that implements the N/M ratio. This segmentation allows each component to be simple while achieving complex overall security through their coordinated interaction.
Solution Approach 2:
The system uses a self-generated random sequence internally to control its own clock signal characteristics. The random number generator and control unit work autonomously to vary N according to the random sequence without requiring external intervention, achieving security while minimizing external complexity.
Data Source
Figure 1~2
Figure 3~4
Figure 5~6
AI summary
The invention relates to a random clock generator comprising an input receiving a master clock signal MCIk, and a clock signal reduction circuit (101) receiving the master clock signal MCIk and a whole number N and supplying an output signal corresponding to a train of N pulses every M clock pulse, M being a whole number higher than 1 and N being a whole number higher than 1 and lower than or equal to M. A number generator (102) and (103) supplies a new number (N) to the clock signal reduction circuit every P pulse of a master clock signal, N and/or P being produced randomly.