Random Clock Generation with Dynamic Pulse Selection for Secure ICs
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Solution Overview
Problem
Current clock signal generators, especially those using pseudo-random components, are either too predictable due to their repetitive nature or too slow and unpredictable, failing to provide an ideal random clock signal for secure applications like secure integrated circuits, which are vulnerable to attacks that exploit clock synchronization.
Innovation Solution
A random clock generator that receives a master clock signal and adjusts it using a clock signal reduction circuit with variables N and P, where N and/or P are randomly generated, allowing control over the frequency of pulses, incorporating a non-linear shift register and random number generator to periodically reset and provide random correction values, ensuring an unpredictable and controlled clock signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Difficulty of detecting and measuring
If a pseudo-random generator is used to mask the clock signal, then the clock signal becomes partially masked and harder to analyze, but the generator remains repetitive and predictable after a certain period of time
Solution Approach 1:
The patent changes the fundamental parameter of randomness from pseudo-random to truly random, while introducing controllable parameters (M, N, P) to manage the unpredictability. This transforms the clock signal from periodically predictable to continuously unpredictable, resolving the contradiction between maskability and reliability.
2Difficulty of detecting and measuring
If a purely random clock generator is used to provide unpredictability, then the clock becomes difficult to analyze, but it is too unpredictable and provides a clock that is far too slow for the required use
Solution Approach 1:
The patent introduces dynamic control parameters (M, N, P) that can be adjusted to optimize the balance between randomness and speed. The system dynamically selects pulse subsets and intervals, allowing the clock to adapt its randomness level to match processing requirements, thus resolving the contradiction between unpredictability and productivity.
Solution Approach 2:
By changing the parameters M (total pulses), N (selected pulses), and P (interval), the system can tune the clock signal characteristics. When high speed is needed, N approaches M; when high security is needed, N is smaller relative to M. This parameter control resolves the fixed trade-off between randomness and speed.
3Object-affected harmful factors
If the clock signal is desynchronised using random-type components to combat attacks, then security against current and electromagnetic analysis is improved, but the clock signal becomes too slow and unpredictable for practical use
Solution Approach 1:
The system dynamically adjusts the randomness level through controllable parameters, allowing optimal security coverage without excessive slowing. The clock can provide sufficient desynchronization to prevent attacks while maintaining adequate processing throughput through parameter optimization.
Solution Approach 2:
The patent uses parameter M to control the overall clock division ratio, parameter N to control the random subset selection, and parameter P to control the refresh interval. By tuning these parameters, the system achieves security against attacks while maintaining practical processing speeds.
Data Source
AI summary
The invention relates to a random clock generator comprising an input receiving a master clock signal MCIk, and a clock signal reduction circuit (101) receiving the master clock signal MCIk and a whole number N and supplying an output signal corresponding to a train of N pulses every M clock pulse, M being a whole number higher than 1 and N being a whole number higher than 1 and lower than or equal to M. A number generator (102) and (103) supplies a new number (N) to the clock signal reduction circuit every P pulse of a master clock signal, N and/or P being produced randomly.