Random-Delay Signal Synchronization for Asynchronous N-Bit Glitch Detection
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Solution Overview
Problem
Existing signal processing devices face errors during asynchronous bit signal processing due to asynchronous clock frequencies, leading to glitches and unwanted delays, especially when synchronizing circuits with different clock frequencies, which are not effectively addressed by prior art using multiple flip-flops.
Innovation Solution
A delay synchronization processing device that generates random numbers to delay asynchronous N-bit signals, allowing for variable clock delays not dependent on the clock frequency, and includes a synchronization processor to perform synchronization processing on the delayed signals, using a combination of flip-flops and switches to manage signal flow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple flip-flops are used for synchronization processing, then synchronization capability is improved, but glitches and unwanted delays occur due to random bit routing
Solution Approach 1:
The patent applies dynamics by making the delay time variable rather than fixed. The delay device dynamically adjusts the delay period based on the random number generated for each bit, allowing flexible routing of bits through different numbers of flip-flops (1 to N flip-flops) to achieve desired synchronization without fixed routing patterns that cause glitches
Solution Approach 2:
The patent changes the parameter of delay time from a fixed value to a variable value determined by random numbers. Each bit is assigned a random delay time (multiple of clock period), which changes the routing path dynamically. This parameter change allows bits to be distributed more evenly across different flip-flop paths, preventing the systematic routing patterns that cause glitches in prior art
2Device complexity
If fixed delay time is used in synchronization processing, then circuit simplicity is improved, but adaptability to different clock frequencies is worsened
Solution Approach 1:
The delay device dynamically selects delay times based on random numbers rather than using a fixed delay path. This dynamic approach allows the same circuit to adapt to different clock frequencies and asynchronous relationships without requiring redesign, while maintaining relatively simple circuit structure through the use of multiplexers and flip-flops
Solution Approach 2:
The patent changes the delay parameter from fixed to variable by introducing random number generation. The delay time is expressed as a variable multiple of the clock period, allowing the circuit to adapt to different asynchronous clock frequency relationships while maintaining a unified circuit structure that works across various frequency combinations
3Reliability
If random delay based on random numbers is implemented, then error detection capability is improved, but device complexity increases
Solution Approach 1:
The patent introduces a random number generation device as an intermediary component that provides random delay values. This intermediary enables error detection capability by creating variable routing patterns that can expose timing-related errors, while the complexity is managed through the use of standard digital components like multiplexers, flip-flops, and random number generators that are readily available in digital design libraries
Data Source
AI summary
The present disclosure relates to a delay synchronization processing apparatus and a signal processing apparatus provided with same. The delay synchronization processing apparatus according to one embodiment of the present disclosure comprises: a delay device to generate a random number and to delay an input asynchronous N-bit signal based on the generated random number; and a synchronization processor configured to perform synchronization processing on the asynchronous N-bit signal delayed by the delay device. Accordingly, errors during non-synchronous bit signal processing can be detected.