Random Edge Injection Locking Circuit for Spur Suppression

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Solution Overview

Problem

Existing injection-locked digital phase locked loops (IL-DPLLs) in Bluetooth Low Energy (BLE) technology face issues with high reference spur and fractional spur due to periodic errors and timing errors between the injection path and PLL path, which are not effectively addressed by current solutions.

Innovation Solution

A circuit and method for random edge injection locking using a digitally controlled delay line and a pulse generator to inject pulses at different phases of the oscillator, breaking repeating patterns and compensating for phase differences to suppress spurs, implemented in a cost-effective manner with smaller area oscillators.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If injection pulses are injected to a fixed phase of the oscillator, then the injection locking is simple to implement, but reference spur and fractional spur are generated due to periodic errors

Engineering Contradiction:
Improveinjection locking implementationVSAvoidreference spur and fractional spur
Core Design Contradiction:
Device complexityVSObject-generated harmful factors

Solution Approach 1:

The patent applies dynamics by making the injection phase variable rather than fixed. The delay line continuously adjusts the phase of injection pulses based on the phase difference between the oscillator output and reference signal, transforming the static fixed-phase injection into a dynamic adaptive process that eliminates periodic errors causing spurs

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent implements feedback by detecting the phase difference between the oscillator output and reference signal, then using this information to adjust the delay line accordingly. This closed-loop feedback mechanism ensures that injection pulses are always applied at the optimal phase to minimize spurious signals while maintaining locking

Inventive Principle:
Principle #23Feedback

2Object-generated harmful factors

If a delay line is used to adjust injection phase dynamically, then reference spur and fractional spur are reduced, but device complexity increases

Engineering Contradiction:
Improvereference spur and fractional spurVSAvoidcircuit structure
Core Design Contradiction:
Object-generated harmful factorsVSDevice complexity

Solution Approach 1:

The patent replaces complex mechanical or analog phase adjustment mechanisms with a digitally controlled delay line. This substitution uses digital control signals to adjust the delay, simplifying the overall system architecture while achieving the same phase adjustment function and reducing spur generation

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

3Adaptability or versatility

If fractional-N mode is used to enable frequency tuning, then frequency flexibility is improved, but periodic error from DTC delay changes introduces fractional spur

Engineering Contradiction:
Improvefrequency tuning capabilityVSAvoidfractional spur
Core Design Contradiction:
Adaptability or versatilityVSObject-generated harmful factors

Solution Approach 1:

The patent converts the harmful periodic error from DTC delay changes into a beneficial effect by using the same delay line to adjust the injection phase. The delay line compensates for the timing errors introduced by fractional-N operation, transforming the source of spurs into a mechanism for eliminating them while preserving frequency tuning flexibility

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Data Source

PatentEP3996280B1Circuit and method for random edge injection locking
Publication Date: 2025.07.23 STICHTING IMEC NEDERLAND
  • EP3996280B1 patent drawingFigure 1
  • EP3996280B1 patent drawingFigure 2
  • EP3996280B1 patent drawingFigure 3

AI summary

A circuit (100) for facilitating random edge injection locking of an oscillator (140) is provided. The circuit comprises a clock signal (101) and a digitally controlled delay line (110), where said digitally controlled delay (110) line is configured to delay the clock signal (101), thereby generating a delayed clock signal (102) . The circuit further comprises an edge selector (120) configured to generate a phase select signal (103) with a random pulse sequence. Moreover, the circuit comprises a pulse generator (130) downstream to the digitally controlled delay line (110) configured to generate injection pulses (104,105) from the delayed clock signal (102) for at least two phases of the oscillator (140) based on the phase select signal (103).