Random Interconnect Structures for Physical Unclonable Functions

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Solution Overview

Problem

Existing interconnect structures for security applications in integrated circuits face challenges in maintaining randomness and stability of binary bits generated by physical unclonable functions (PUFs) due to distortion from operating conditions, requiring complex sensing circuits.

Innovation Solution

A method involving the formation of a sacrificial masking layer with randomly distributed particles, etching to create conductive features with a random distribution, and filling dielectric layers to define conductive features that provide random electrical shorts, embodying a simple and compact physical unclonable function.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If active device structures are used to generate binary bits for PUF, then the PUF can produce responses, but the responses are distorted by operating conditions such as voltage and temperature requiring complicated sensing circuits

Engineering Contradiction:
Improvestability of binary bitsVSAvoidsensing circuits
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent replaces active device structures (electronic components requiring complex sensing) with passive interconnect structures (metal lines and vias). The binary bits are generated by the physical presence or absence of conductive material in specific locations, detected through simple electrical continuity measurements rather than complex sensing circuits. This substitution eliminates sensitivity to voltage and temperature variations while simplifying the overall device architecture.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent changes the fundamental parameter used for PUF generation from active device electrical characteristics (which vary with operating conditions) to the physical geometry and connectivity of passive interconnect structures. The binary bits are determined by whether conductive features are present or absent in specific locations, a parameter that remains stable across different voltage and temperature conditions.

Inventive Principle:
Principle #35Parameter changes

2Manufacturing precision

If conventional lithography is used to form PUF structures, then manufacturing processes are standardized, but the randomness and uniqueness of PUF responses are compromised

Engineering Contradiction:
Improvepattern formationVSAvoidrandomness of binary bits
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The patent introduces a sacrificial masking layer with randomly distributed particles before the standard lithography process. This preliminary random structure guides the subsequent etching and material deposition, ensuring that the final PUF pattern contains inherent randomness from the particle distribution while still benefiting from the precision of conventional lithography for forming the interconnect structures.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The sacrificial masking layer acts as an intermediary element that transfers randomness to the final PUF structure. The randomly distributed particles in the masking layer serve as templates that define the random connectivity pattern of the interconnect structures, while the standard lithography and etching processes provide the manufacturing precision needed for reliable fabrication.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS10297546B2Interconnect structures for a security application
Publication Date: 2019.05.21 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US10297546B2 patent drawing
  • US10297546B2 patent drawing
  • US10297546B2 patent drawing

AI summary

Interconnect structures for a security application and methods of forming an interconnect structure for a security application. A sacrificial masking layer is formed that includes a plurality of particles arranged with a random distribution. An etch mask is formed using the sacrificial masking layer. A hardmask is etched while masked by the etch mask to define a plurality of mask features arranged with the random distribution. A dielectric layer is etched while masked by the hardmask to form a plurality of openings in the dielectric layer that are arranged at the locations of the mask features. The openings in the dielectric layer are filled with a conductor to define a plurality of conductive features.