Random Number Generating Circuit Using Feedback XOR Logic
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Solution Overview
Problem
Existing random number generating circuits face variability in performance due to manufacturing variations and oscillation timing, leading to reduced entropy and potential generation of non-random data, especially when signals are consistently high or low.
Innovation Solution
A random number generating circuit design comprising multiple oscillating circuits, latch circuits, exclusive OR circuits, and a shift register, where the output of each oscillating circuit is fed back through exclusive OR circuits and converted into parallel data using a secondary clock with a lower frequency than the primary clock, ensuring high-entropy data generation even when some oscillating circuits fail to produce random outputs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single oscillating circuit is used to generate random data, then the circuit complexity is low, but the entropy of generated data varies significantly due to manufacturing variation and may become zero if the signal is always high or low
Solution Approach 1:
The patent divides the random data generation function into multiple independent oscillating circuits (first to N-th oscillating circuits). Each circuit operates independently and its output is latched and processed separately. This segmentation ensures that if one circuit produces low-entropy data due to manufacturing variation, other circuits can compensate, thereby maintaining overall system reliability and entropy.
2Reliability
If multiple oscillating circuits are used to improve entropy, then the reliability of data generation is improved, but the device complexity increases
Solution Approach 1:
The patent combines the outputs of multiple oscillating circuits through latch circuits and exclusive OR circuits. The first to N-th latch circuits latch the outputs of respective oscillating circuits, and subsequent exclusive OR circuits combine these latched outputs. This merging approach maintains high entropy while providing a systematic structure that manages the complexity of multiple circuits through standardized combination logic.
Solution Approach 2:
The patent implements feedback mechanisms where the output of exclusive OR circuits is fed back through additional latch circuits ((N+1)-th to (2×N)-th latch circuits) and combined again through an (N+1)-th exclusive OR circuit. This feedback structure ensures that influences of all data outputs are retained and processed multiple times, enhancing entropy while using a systematic approach to manage circuit complexity.
3Productivity
If the oscillation frequency is increased to improve generation efficiency, then the productivity of random data generation is improved, but the amount of jitter decreases which reduces entropy
Solution Approach 1:
The patent uses a periodic clock signal with a lower frequency than the oscillation signals to latch the outputs of oscillating circuits. This periodic action at a controlled frequency ensures that the latching occurs at optimal moments to capture jitter, maintaining entropy while achieving efficient data generation. The shift register also uses this lower frequency clock to convert serial data to parallel data, balancing speed and quality.
4Reliability
If a smoothing circuit is added to improve data quality, then the reliability of random data is improved, but the device complexity increases and the circuit becomes useless if the signal is always high or low
Solution Approach 1:
The patent performs preliminary processing of oscillation signals by latching them at specific clock timings before further processing. The first to N-th latch circuits latch the outputs of oscillating circuits at timings determined by the lower frequency clock, ensuring that jitter is captured before any smoothing or combination operations. This preliminary latching action ensures that even if subsequent smoothing circuits are used, the fundamental randomness is already preserved.
Data Source
AI summary
According to one embodiment, a random number generating circuit includes first to N-th oscillating circuits (N is a natural number equal to 2 or greater), first to N-th latch circuits that latch outputs of the first to N-th oscillating circuits by a first clock having a first frequency, first to N-th exclusive OR circuits, (N+1)-th to (2×N)-th latch circuits that latch outputs of the first to N-th exclusive OR circuits by the first clock, an (N+1)-th exclusive OR circuit that outputs an exclusive OR of outputs of the (N+1)-th to (2×N)-th latch circuits, and an M-bit shift register that converts serial data output from the (N+1)-th exclusive OR circuit into M-bit parallel data (M is a natural number equal to 2 or greater) by a second clock having a second frequency.