Random Number Generator Using Prime-Length Inverter Chains

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Solution Overview

Problem

Conventional random number generators are large, inefficient, and lack physical security, making them unsuitable for high-rate generation of truly random numbers in limited spaces, especially in cryptographic applications where physical security is required.

Innovation Solution

A random number generator using multiple oscillators with inverter chains of different prime lengths, combined through combinatorial logic to generate truly random numbers, which are then processed by a synchronous sampling clock to ensure entropy and lack inherent patterns.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional entropy generators using complex sensors are used, then truly random numbers can be generated, but the device occupies large space and generates numbers at low rate

Engineering Contradiction:
Improvetrue randomnessVSAvoidnumber generation rate
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent replaces physical entropy sources (radioactive decay, thermal noise) with a digital oscillator system. Multiple oscillators with different prime numbers of inverters generate random bits through their inherent timing variations and phase relationships, eliminating the need for complex physical sensors while achieving high generation rates.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent changes the fundamental parameter of randomness generation from physical processes to digital signal processing. By using oscillators with different prime numbers of inverters, the system creates deterministic variations in timing and phase that manifest as random bits, achieving both high rate and true randomness.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If conventional entropy generators are used, then truly random numbers can be generated, but the device is exposed to external monitoring and lacks physical security

Engineering Contradiction:
Improvetrue randomnessVSAvoidphysical security
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent extracts the randomness generation function from exposed physical sensors and implements it within a secure, enclosed digital circuit. The oscillators and combinatorial logic are contained within a protected hardware environment, eliminating external monitoring capabilities while maintaining true randomness through internal digital processes.

Inventive Principle:
Principle #2Taking out (Extraction)

3Productivity

If whiteners using hash functions are used, then number generation rate increases, but the generated numbers still lack inherent randomness and patterns

Engineering Contradiction:
Improvenumber generation rateVSAvoidtrue randomness
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

Instead of using a whitener to process pseudo-random output, the patent inverts the approach by generating truly random bits directly from oscillator timing variations. The combinatorial logic combines signals from multiple oscillators with different prime numbers of inverters to produce random bits that inherently lack patterns, eliminating the need for subsequent whitening stages.

Inventive Principle:
Principle #13The other way round (Inversion)

Data Source

PatentUS9058228B2Random number generator for generating truly random numbers
Publication Date: 2015.06.16 RAYTHEON CO
  • US9058228B2 patent drawing
  • US9058228B2 patent drawing
  • US9058228B2 patent drawing

AI summary

An apparatus includes multiple oscillators, where each oscillator includes an inverter chain. The apparatus also includes combinatorial logic configured to generate a random number having one or more bits. The combinatorial logic is configured to generate each bit by combining two or more signals from at least two oscillators that have inverter chains with different prime numbers of inverters. The combinatorial logic may be configured to generate each bit using signals from a unique combination of oscillators. The combinatorial logic may also be configured to combine the signals asynchronously and sample the combined signal synchronously using a synchronous sampling clock, where at least one of the signals is not harmonically related to the sampling clock. Each of at least one of the oscillators may include multiple taps configured to provide multiple signals, and the multiple signals from one oscillator could have different asynchronous phases relative to the sampling clock.