Random Number Test Circuit Using Segmented Serial Processing
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Solution Overview
Problem
Conventional random number test circuits require a large number of data bits and a substantial circuit scale to operate effectively, making them unsuitable for small-sized information terminals, as they need to handle extensive data for each test cycle, leading to an enormous circuit area.
Innovation Solution
A random number test circuit design that uses a shift register, comparison circuit, counter, and decision circuit to assess the quality of random numbers by comparing serial numbers with delayed versions, employing a reduced data processing approach that eliminates the need for converting serial to parallel and back, thereby minimizing circuit size without compromising test accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional FIPS-140-2 test methods are implemented as circuits, then test accuracy is improved, but circuit scale becomes very large
Solution Approach 1:
The patent segments the random number test into multiple independent test items (monobit test, poker test, runs test, long runs test) that can be performed sequentially on smaller data portions. Each test item processes a subset of the 20000-bit data independently, allowing the circuit to handle large data volumes without requiring all data to be held simultaneously, thus reducing circuit scale while maintaining test accuracy.
Solution Approach 2:
The patent performs preliminary data preparation by dividing the 20000-bit random number data into multiple segments before testing. The circuit prepares test data in advance by selecting and organizing subsets of data for each test item, which allows sequential processing without requiring enormous simultaneous data storage capacity.
2Reliability
If 20000-bit data is held for testing, then test completeness is improved, but hold circuit size becomes enormous
Solution Approach 1:
The patent divides the 20000-bit data into multiple segments and processes them sequentially through different test items. Instead of holding all 20000 bits simultaneously, the circuit holds only the necessary portion for each specific test item at any given time, dramatically reducing the hold circuit area while maintaining test completeness through systematic sequential processing.
Solution Approach 2:
The patent employs periodic action by cycling through multiple test items in sequence, with each test item processing a specific portion of the data. The circuit periodically switches between different test methods (monobit, poker, runs, long runs tests), allowing comprehensive testing without requiring all data to be held simultaneously.
3Reliability
If multiple test methods are implemented simultaneously, then test thoroughness is improved, but circuit area increases
Solution Approach 1:
The patent segments the testing process into distinct test items that are executed sequentially rather than simultaneously. Each test item (monobit, poker, runs, long runs) is implemented as a separate functional block that processes data independently, allowing thorough multi-method testing while minimizing circuit area by avoiding simultaneous operation of all test methods.
Solution Approach 2:
The patent implements dynamic switching between different test methods based on processing requirements. The circuit dynamically selects which test item to execute next and adjusts its operation accordingly, rather than maintaining all test methods active simultaneously. This dynamic approach achieves test thoroughness while optimizing circuit area utilization.
Data Source
AI summary
The random number test circuit includes a shift register which operates based on a clock and which successively stores serial random numbers generated by a random number generation element, a first random number being output from a predetermined stage of the shift register; a comparison circuit which compares the first random number with a second random number located at a distance of a first predetermined number of bits from the first random number, the second random number being generated by the random number generation element; a counter which counts a frequency of occurrence of equality or inequality between the first random number and the second random number, with respect to all bits in the serial random numbers, and a decision circuit which judges an article quality to be good if a count value in the counter indicates a frequency of occurrence equal to or less than a number determined previously by correlation.