Random Pattern Testing Logic Structures Fault Coverage
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Solution Overview
Problem
Existing random pattern testing methods for logic structures face challenges in achieving 100% fault coverage, particularly in detecting defects in critical late mode timing paths, due to linear dependencies and difficulties in testing these paths effectively.
Innovation Solution
The method involves identifying and analyzing the functional behavior of logic structures, modifying the circuit configuration to frequently exercise critical timing paths, and generating test patterns to ensure thorough testing, including routing parallel data paths and configuring shared data manipulation logic between registers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional scan chains are used for random pattern testing, then test coverage is achieved, but critical late mode timing paths are not frequently tested
Solution Approach 1:
The patent applies preliminary action by pre-configuring parallel data paths and selecting specific registers to load data before the actual testing occurs. This allows critical timing paths to be prepared and exercised more frequently without waiting for random patterns to naturally exercise them, thereby improving both fault coverage and testing frequency of critical paths simultaneously
2Device complexity
If multiple registers are fed from the same random source, then testing is simplified, but linear dependencies occur reducing test effectiveness
Solution Approach 1:
The patent segments the single random source into multiple independent random sources, each feeding specific registers. This segmentation eliminates linear dependencies between registers while maintaining manageable complexity through systematic organization of the segmented sources and their associated select mechanisms
3Reliability
If 100% fault coverage is targeted, then comprehensive testing is achieved, but testing time and complexity increase significantly
Solution Approach 1:
The patent applies partial action by using multiple shadow registers to selectively test critical timing paths with higher frequency while using fewer registers for non-critical paths. This partial focusing on critical areas achieves comprehensive fault coverage without requiring equal testing effort across all paths, thereby reducing overall testing time while maintaining 100% fault coverage
Data Source
AI summary
A test method and apparatus for randomly testing logic structures. The method includes identifying and analyzing a functional behavior of a logic structure to be covered during the random testing, modifying the logic structure such that the logic structure behaves in a functional manner during random testing, and generating patterns to exercise the modified logic structure.