Random Polygonal Mesh Pattern for Touch Panel Conductive Film
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In touch panels with irregular polygonal metal meshes, electrode intersections lead to high parasitic capacitance, reducing detection sensitivity and responsiveness due to moire interference with display device pixel patterns.
Innovation Solution
A method for designing a mesh pattern with overlapping conductive layers featuring random polygonal cells, where the first conductive layer includes a first mesh pattern of tightly disposed polygons and a second conductive layer includes a second mesh pattern formed by connecting arbitrary points within these polygons, reducing parasitic capacitance and improving sensitivity and responsiveness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If an irregular polygonal metal mesh is used as electrodes, then moire interference with display device pixel patterns is reduced, but parasitic capacitance at electrode intersections increases, reducing detection sensitivity and responsiveness
Solution Approach 1:
The patent applies asymmetry by using irregular polygonal cells with varying shapes and sizes in the mesh pattern, rather than uniform regular polygons. This asymmetric design disrupts the periodicity that causes moire interference with display pixel patterns, while carefully controlling the intersection geometry to manage parasitic capacitance effects
Solution Approach 2:
The patent implements local quality by varying the polygonal cell characteristics (shape, size, orientation) in different regions of the mesh pattern. This allows optimization of local areas to minimize both moire interference and parasitic capacitance accumulation, creating zones with different geometric properties to balance the two competing requirements
2Object-affected harmful factors
If an irregular polygonal metal mesh is used as electrodes, then moire interference with display device pixel patterns is reduced, but responsiveness deteriorates due to high parasitic capacitance
Solution Approach 1:
The asymmetric irregular polygonal design breaks the periodic correlation between the mesh and display pixels, eliminating moire while the varied geometry distributes capacitance more evenly, preventing localized capacitance buildup that would slow response
Solution Approach 2:
The patent changes geometric parameters (polygon side lengths, angles, areas) across the mesh structure to optimize the balance between moire reduction and capacitance management, adjusting these parameters to achieve both anti-moire performance and acceptable responsiveness
Data Source
AI summary
A method of designing a mesh pattern includes: a first step of tightly disposing a plurality of polygons having an arbitrary shape in an area to form a transparent active area; a second step of obtaining a circumcenter of each of the polygons; a third step of disposing one arbitrary point in each of the polygons to be positioned at a distance, which is less than ½ a radius of a circumscribed circle of the polygon, from the circumcenter; a fourth step of forming a pattern to form second cells by connecting two arbitrary points corresponding to two polygons that share each of sides of the polygons; and a fifth step of forming a pattern to form first cells using the polygons, in which the polygons having a random shape are disposed in the first step, and/or the arbitrary point is randomly disposed in the third step.