Random Pre-charge Circuit Topology for Side-Channel Attack Resistance
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Solution Overview
Problem
Existing cryptographic systems are vulnerable to side-channel attacks, such as simple power analysis (SPA) and differential power analysis (DPA), which exploit power dissipation and electromagnetic noise to infer sensitive information.
Innovation Solution
A circuit topology that alternates between valid and random data inputs to combinatorial logic and latch stages, generating randomized power dissipation and electromagnetic noise, making it difficult for attackers to correlate side-channel information with the circuit's inputs, outputs, and stored values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If random data is alternately provided to combinatorial logic and latch stages, then resistance to side-channel analysis is enhanced, but circuit complexity increases
Solution Approach 1:
The patent implements periodic alternation between valid data and random noise data fed to combinatorial logic and latch stages. This periodic injection of random data during clock cycles creates randomized power dissipation patterns that mask side-channel information, enhancing security while maintaining regular circuit operation
Solution Approach 2:
The patent introduces random data as an intermediary element that mediates between the cryptographic operations and the power analysis attack. This random data acts as noise that interferes with the correlation between power consumption and sensitive cryptographic operations, protecting the system without modifying the core cryptographic logic
2Reliability
If random data inputs are provided to generate noise, then power analysis resistance is improved, but power dissipation increases
Solution Approach 1:
The patent applies partial action by injecting random data only during specific clock cycles or for specific latch stages, rather than continuously across the entire circuit. This selective noise injection provides sufficient masking effect while limiting the additional power consumption to only the portions of the circuit where it is most effective
Data Source
AI summary
A side-channel attack resistant circuit topology for performing logic functions. This topology includes combinatorial logic to perform the at least one logic function. A logic input selector alternately supplies, in response to a first timing reference signal, an input to the combinatorial logic with noise generating input values and valid input values. A first latch input selector alternately supplies, in response to the first timing reference signal, a first memory element input with noise generating input values and valid logic output values. The valid logic output values are received from the combinatorial logic. A first memory element latches the valid logic output values in response to a second timing reference signal.