Random-Reset CDAC Circuit for Glitch and SNR Control
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Solution Overview
Problem
Conventional capacitor digital-to-analog converters (CDACs) face issues with glitches during the reset phase due to periodic reset operations, which affect signal integrity and lead to specific frequency components in the output, especially in high-performance applications requiring high resolution and frequency, such as wireless Bluetooth modems.
Innovation Solution
The implementation of a capacitor digital-to-analog converter that utilizes a random reset control signal, irregularly toggled during the reset phase, to minimize glitches by randomly generating rising and falling edges, thereby reducing signal dependence and eliminating periodic frequency components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a periodic reset control signal is used to initialize the summation node, then the reset operation can be performed regularly, but glitches occur at specific frequency components due to periodic toggling
Solution Approach 1:
The patent applies periodic action by using a regularly toggled reset control signal generated from the internal clock signal to initialize the summation node at specific intervals. This periodic reset operation ensures reliable initialization while the randomization element is introduced through the random reset control signal generator that selectively activates resets based on input signal characteristics, thereby reducing periodic glitches.
Solution Approach 2:
The patent implements dynamics by transitioning from a static periodic reset approach to a dynamic reset mechanism. The random reset control signal generator dynamically adjusts the reset timing based on the input digital signal characteristics, making the reset operation adaptive rather than purely periodic. This dynamic approach reduces periodic glitches while maintaining initialization reliability.
2Device complexity
If a regular toggle reset signal is used, then the reset timing is predictable and simple to generate, but signal dependency increases and SNR characteristics deteriorate
Solution Approach 1:
The patent introduces an intermediary component - the random reset control signal generator - that sits between the simple periodic reset signal source and the summation node. This intermediary processes the periodic reset signal by randomizing its activation timing based on input signal characteristics, thereby improving SNR characteristics while maintaining reasonable complexity through a modular design.
Solution Approach 2:
The patent applies parameter changes by modifying the timing parameter of the reset signal from a fixed periodic pattern to a randomized pattern. The random reset control signal generator changes the temporal parameters of reset activation based on input signal analysis, thereby improving SNR characteristics without significantly increasing overall system complexity.
3Reliability
If the reset phase is extended to improve initialization, then more thorough resetting is achieved, but the conversion phase timing is compressed and productivity decreases
Solution Approach 1:
The patent applies partial action by performing reset operations selectively rather than continuously. The random reset control signal generator activates resets only when necessary based on input signal characteristics, avoiding unnecessary reset operations that would consume time. This partial reset approach maintains initialization reliability while preserving conversion phase throughput.
Solution Approach 2:
The patent implements preliminary action by performing rapid initialization of the summation node at the beginning of each conversion cycle using the periodic reset signal. This preliminary reset ensures the node is properly initialized before the conversion phase begins, allowing the conversion phase to proceed without delay while maintaining initialization completeness.
Data Source
AI summary
A capacitor digital-to-analog converter (CDAC) includes a clock generator, a random reset control signal generator, a first capacitor array, a first reset circuit and an output buffer. The clock generator generates an internal clock signal and a reset control signal that are regularly toggled. The random reset control signal generator generates a random reset control signal that is irregularly toggled. The first capacitor array includes a plurality of capacitors connected to a first summation node, and generates a first summation voltage corresponding to a first input digital signal based on first and second reference voltages. The first reset circuit initializes the first summation node based on the random reset control signal. The output buffer generates a first analog output voltage by buffering the first summation voltage.