Randomized 3D Interconnect Obfuscation for Reverse Engineering Protection

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Solution Overview

Problem

Electronic circuits are vulnerable to reverse engineering due to their complex interconnect patterns, which can be deconstructed to reveal underlying circuitry and compromise intellectual property.

Innovation Solution

Generating randomized electrical interconnects by creating a three-dimensional grid, selecting random path directions and lengths for each interconnect, and adding noise to the interconnect paths, making it difficult to reverse engineer the circuit.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional electrical interconnect patterns are used, then circuit functionality is achieved, but the circuit is vulnerable to reverse engineering

Engineering Contradiction:
Improveprotection against reverse engineeringVSAvoidinterconnect pattern complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent introduces a third dimension (Z-axis) to the traditional two-dimensional interconnect routing by utilizing vias to connect different conductive layers. This vertical dimension allows interconnects to change layers, creating three-dimensional routing paths that are significantly more difficult to reverse engineer while maintaining circuit functionality.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent divides the interconnect structure into multiple segments across different conductive layers, with each segment connected via vias. This segmentation creates complex, non-linear paths that obscure the direct relationship between input and output nodes, making reverse engineering much more difficult while still achieving the required electrical connections.

Inventive Principle:
Principle #1Segmentation

2Reliability

If randomized paths are generated for interconnects, then obfuscation is improved, but manufacturing precision requirements increase

Engineering Contradiction:
Improveobfuscation effectivenessVSAvoidvia placement precision
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent varies multiple parameters including the number of conductive layers, via positions, interconnect lengths, and path routing patterns. By changing these parameters in a controlled manner, the system achieves high obfuscation effectiveness while maintaining manufacturability through systematic design rules and constraints.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The randomized interconnect structure serves multiple functions simultaneously: it provides electrical connectivity, achieves obfuscation against reverse engineering, and maintains manufacturability through standardized via and trace patterns. The same basic structure adapts to different circuit requirements by varying the randomization parameters within design constraints.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS11288434B2System and method for obfuscation of electronic circuits
Publication Date: 2022.03.29 HONEYWELL FEDERAL MANUFACTURING & TECHNOLOGIES LLC
  • US11288434B2 patent drawing
  • US11288434B2 patent drawing
  • US11288434B2 patent drawing

AI summary

A computer-implemented method of generating randomized electrical interconnects for an electronic circuit comprises steps of receiving a netlist of nodes of electronic components to be connected, each connection between the nodes forming an electrical interconnect; determining a list of one or more path directions for each electrical interconnect; determining a plurality of path direction distances for each electrical interconnect; generating a plurality of segments for each electrical interconnect, each segment having one path direction and a length which are selected at random; calculating a sum of the lengths of all segments of the plurality of segments in each path direction each time a segment is generated for each electrical interconnect; removing one path direction from the list of path directions when a first condition is met; and stopping the generating a plurality of segments for each electrical interconnect when a second condition is met.