Randomized Clock Division With Drift Control for FIFO Stability
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Solution Overview
Problem
In mixed signal systems, digital clock spur coupling to analog modules can cause operational issues, with existing methods either leading to unbounded clock drift due to pseudorandom division or poor spur attenuation with fixed sequences, resulting in FIFO overflow/underflow.
Innovation Solution
A digital clock generation method using a drift-corrected randomizing sequence of clock division factors, generated through a combination of input randomizing sequences and accumulated drift correction, to bound clock drift based on a selected FIFO depth, implemented in a circuit with division selector and arbitration circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If pseudorandom division of source clock is used, then digital clock spurs are suppressed, but clock drift becomes unbounded causing FIFO overflow/underflow
Solution Approach 1:
The patent implements a feedback mechanism by monitoring the FIFO watermarks (read/write pointers) and adjusting the clock division factors accordingly. When the FIFO approaches overflow or underflow conditions, the system modifies the random division sequence to reduce drift accumulation, thereby maintaining FIFO stability while preserving spur suppression benefits
Solution Approach 2:
The patent transitions from static fixed division to dynamic random division with adaptive control. The clock division factors are selected from multiple possible values (e.g., N-1, N, N+1) based on real-time FIFO status, creating a dynamic system that adapts to maintain bounded drift while suppressing spurs
2Reliability
If fixed sequence division is used, then clock drift is bounded, but low frequency spurs have poor attenuation
Solution Approach 1:
The patent changes the division parameter from a fixed value to a randomized sequence of values (N-1, N, N+1). This parameter variation suppresses low frequency spurs through spectral spreading while the feedback control ensures the randomization remains bounded to prevent FIFO overflow/underflow
3Reliability
If FIFO depth is increased to prevent overflow/underflow, then reliability improves, but area consumption increases
Solution Approach 1:
The feedback control mechanism allows the system to maintain FIFO stability with smaller depth by actively managing drift accumulation. The watermarks trigger adjustments to division factors that prevent extreme drift buildup, enabling reduced FIFO depth while maintaining reliability
Data Source
AI summary
A digital clock generator for a digital clock domain interfaced to another clock domain through a FIFO, includes division selector circuitry to provide an input randomizing sequence of clock division factors, selected from a defined set of clock division factors corresponding to a target average clock division, and division arbitration circuitry to generate a drift-corrected randomizing sequence of clock division factors, based at least in part on the input randomizing sequence of clock division factors, and an accumulated drift correction signal. A clock drift control loop generates the accumulated drift correction signal, based at least in part on an accumulated clock drift relative to the target average clock division. Clock generation can be based on randomized division with the drift-corrected randomizing sequence of clock division factors. The drift-corrected randomizing sequence of clock division factors can be generated so that clock drift is bounded based on a FIFO depth.