Randomized Memory Addressing for Secure In-Memory Computation
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Solution Overview
Problem
In-memory computation (IMC) processing systems are vulnerable to side channel attacks due to the static nature of computational weight data storage, which makes it susceptible to extraction.
Innovation Solution
Implement a randomized scrambling of row and column addressing in the memory array to obfuscate the access pattern, using an address scrambling circuit to randomize the order of addresses for accessing memory cells during in-memory computation operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If computational weight data is stored in a stationary manner in the memory array, then memory utilization is optimized and computation can be performed efficiently, but the data becomes susceptible to side channel attacks for extraction
Solution Approach 1:
The patent applies dynamics by transitioning from a stationary memory access pattern to a dynamic randomized access pattern. The address scrambling circuit randomly permutes the row address sequence during memory operations, making the access pattern non-predictable and thus resistant to side channel attacks while maintaining computational efficiency through in-memory operations
2Ease of operation
If a stationary approach to computational weight data storage is implemented, then the memory array can be accessed efficiently for in-memory computation, but the proprietary information becomes easier to extract through side channel attacks
Solution Approach 1:
The patent introduces an intermediary component - the address scrambling circuit - between the memory controller and the memory array. This intermediary randomly permutes row addresses before data is accessed, serving as a mediator that protects proprietary weight data from side channel attacks while allowing efficient in-memory computation to proceed
3Loss of energy
If computational weight data is kept static in the memory array, then the in-memory computation operation can execute efficiently without data movement, but the static nature of the data makes it vulnerable to power analysis attacks
Solution Approach 1:
The patent resolves this contradiction by implementing dynamic address scrambling that randomizes the sequence of row accesses. This dynamic approach prevents predictable power consumption patterns that would otherwise expose computational weight data to power analysis attacks, while maintaining the in-memory computation efficiency and low power consumption characteristic
Data Source
AI summary
Computational weight data for an in-memory computation operation is stored in memory cells of a memory array. During execution of the in-memory computation operation, the computational weight data is read from the memory array using a randomly selected order of row and/or column access. A digital computation processing circuit receives feature data for the in-memory computation operation and performs a computational operation as a function of the feature data and the read computational weight data. A map signal generated in response to the memory access provides information specifying the randomly scrambled order of access. the digital computation processing circuit uses that information to map the retrieved computational weight data to the feature data when performing the computational operation for the in-memory computation operation.