Randomized Memory Addressing for Secure In-Memory Computing
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Solution Overview
Problem
In-memory computation processing systems are vulnerable to side channel attacks due to the static nature of computational weight data, making it susceptible to extraction.
Innovation Solution
Implement a randomized scrambling of row and/or column addressing in the memory array to obfuscate the access pattern, combined with a digital computation processing circuit to properly map the scrambled data for secure in-memory operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If computational weight data is stored statically in memory cells for in-memory computation operations, then computational efficiency is improved by eliminating data transfer between memory and computing devices, but security deteriorates making the data susceptible to side channel attack extraction
Solution Approach 1:
The patent applies dynamics by transforming the static storage approach into a dynamic one. Memory cells that previously held fixed computational weight data are now dynamically reconfigured through row and column scrambling. The same physical memory locations are reused for different logical weight values across multiple computation operations, creating continuously changing access patterns that prevent side channel attacks while maintaining in-memory computation efficiency.
Solution Approach 2:
The patent changes the addressing parameters (row and column indices) through scrambling functions. Instead of directly accessing memory at fixed addresses corresponding to weight data, the system applies scrambling transformations to these addresses. This parameter change ensures that the same physical memory cell may represent different logical weight values at different times, securing the data against extraction attacks while preserving computational functionality.
2Object-affected harmful factors
If row and column addressing is randomized through scrambling, then security is improved by obfuscating access patterns and protecting against side channel attacks, but device complexity increases due to the need for address scrambling circuits and computation mapping logic
Solution Approach 1:
The patent achieves universality by designing the scrambling mechanism to serve multiple functions simultaneously. The same row and column scrambling circuits that provide security obfuscation also enable efficient in-memory computation by maintaining the mathematical relationships needed for MAC operations. Additionally, the scrambled addressing scheme supports both weight data storage and feature data access, reducing the need for separate security and computation pathways.
Solution Approach 2:
The patent introduces scrambling circuits as intermediary components between the conventional memory addressing interface and the physical memory array. These intermediary circuits transform standard addresses into scrambled addresses for memory access, and transform scrambled computation results back into standard formats. This intermediary layer provides the necessary complexity for security while keeping the rest of the system architecture relatively simple and compatible with existing memory interfaces.
Data Source
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AI summary
Computational weight data for an in-memory computation operation is stored in memory cells of a memory array. During execution of the in-memory computation operation, the computational weight data is read from the memory array using a randomly selected order of row and/or column access. A digital computation processing circuit receives feature data for the in-memory computation operation and performs a computational operation as a function of the feature data and the read computational weight data. A map signal generated in response to the memory access provides information specifying the randomly scrambled order of access. the digital computation processing circuit uses that information to map the retrieved computational weight data to the feature data when performing the computational operation for the in-memory computation operation.