Randomized Modular Polynomial Reduction for Hardware Security
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Solution Overview
Problem
Existing cryptographic algorithms face challenges in securing modular reduction operations of polynomials in finite fields against cryptoanalysis attacks while maintaining speed and accuracy, particularly in resisting power analysis and timing attacks.
Innovation Solution
A computer-implemented method for modular reduction of polynomials in a binary finite field GF(2n) that estimates the polynomial quotient using a precomputed scaled inverse of the polynomial modulus, injecting random error into the quotient estimation to enhance security, while ensuring mathematical equivalence and accuracy through final strict reduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If deterministic modular reduction is used, then computational accuracy is ensured, but security against cryptoanalysis attacks deteriorates
Solution Approach 1:
The patent applies dynamics by making the modular reduction process variable rather than fixed. A random value r is introduced into the quotient estimation, causing the computation path to vary dynamically while maintaining mathematical correctness. This prevents attackers from predicting computational patterns that would exist in deterministic algorithms.
Solution Approach 2:
The patent changes the parameter of quotient estimation by adding a random component r to the estimated quotient q. This parameter modification transforms the deterministic computation into a randomized one, maintaining accuracy through mathematical equivalence while introducing variability that secures against cryptoanalysis.
2Reliability
If traditional modular reduction methods are used, then security considerations are addressed, but computational speed deteriorates
Solution Approach 1:
The patent applies preliminary action by pre-computing the scaled inverse of the modulus and storing it for reuse. This pre-computation step enables faster quotient estimation during actual modular reduction operations, improving computational speed while maintaining security through the randomized estimation approach.
Solution Approach 2:
The patent substitutes the traditional mechanical division operation with a multiplication-based quotient estimation using the precomputed scaled inverse. This replacement of division (a slower operation) with multiplication (a faster operation) significantly improves computational speed while the randomized estimation maintains security properties.
3Productivity
If quotient estimation is simplified, then computational speed improves, but estimation accuracy deteriorates
Solution Approach 1:
The patent modifies the estimation approach by using a scaled inverse and introducing a random parameter r, which allows for faster computation while maintaining sufficient accuracy for the modular reduction process. The randomness actually helps by distributing estimation errors in a controlled manner that preserves correctness.
Solution Approach 2:
The patent introduces an intermediary scaled inverse value that facilitates faster quotient estimation. This intermediary computation serves as a mediator between the dividend and modulus, enabling speed improvement while the subsequent adjustment using random r ensures the final result maintains mathematical accuracy.
Data Source
AI summary
A cryptographically secure, computer hardware-implemented binary finite-field polynomial modular reduction method estimates and randomizes a polynomial quotient used for computation of a polynomial remainder. The randomizing error injected into the approximate polynomial quotient is limited to a few bits, e.g. less than half a word. The computed polynomial remainder is congruent with but a small random multiple of the residue, which can be found by a final strict binary field reduction by the modulus. In addition to a computational unit and operations sequencer, the computing hardware also includes a random or pseudo-random number generator for producing the random polynomial error. The modular reduction method thus resists hardware cryptoanalysis attacks, such as timing and power analysis attacks.