Range Checking Instruction for Memory Access Verification
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Solution Overview
Problem
Existing data processing systems face inefficiencies in security checking operations due to the need to individually verify access permissions for each memory address, which can lead to increased latency and code size, especially in real-time critical applications with variable-sized memory regions.
Innovation Solution
A range checking instruction is introduced that allows software to determine whether two addresses correspond to the same memory attribute entry, simplifying security checks by returning a status value indicating access permissions for a range of addresses, thereby reducing the number of instructions required and improving performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If individual address verification is performed for each memory address, then access permission checking accuracy is improved, but checking latency increases
Solution Approach 1:
The patent combines multiple address verification operations into a single bulk verification instruction. The range checking instruction allows simultaneous verification of multiple addresses against memory attribute entries, returning a consolidated status value that indicates whether all addresses in a range satisfy access permissions. This merging approach maintains verification accuracy while significantly reducing checking latency by performing operations in parallel rather than sequentially.
2Measurement precision
If individual address verification is performed for each memory address, then access permission checking accuracy is improved, but code size increases
Solution Approach 1:
The patent introduces a range checking instruction that consolidates multiple verification operations into a single instruction. Instead of requiring separate instructions for each address verification, the bulk verification operation performs checks on multiple addresses simultaneously and returns a unified status value. This reduces code size by eliminating redundant verification instructions while maintaining the accuracy of access permission checking through comprehensive range validation.
3Productivity
If variable-sized memory attribute entries are supported, then address region coverage efficiency is improved, but determination complexity increases
Solution Approach 1:
The patent employs parameter changes by introducing a range checking instruction that accepts address parameters (base address and offset) to define verification ranges. The instruction decoder extracts these parameters and uses them to configure the verification operation. This approach maintains efficiency in covering variable-sized address regions while managing determination complexity through standardized parameter extraction and range calculation logic in the instruction decoder.
4Loss of time
If bulk verification of access permissions is performed, then checking latency is reduced, but instruction complexity increases
Solution Approach 1:
The patent segments the bulk verification operation into distinct functional components: parameter extraction by the instruction decoder, range calculation logic, parallel verification execution, and status value generation. This segmentation manages instruction complexity by organizing the bulk verification process into modular, manageable stages while achieving reduced latency through parallel processing of address verifications against memory attribute entries.
Data Source
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Figure 2
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AI summary
An apparatus (2) comprises: an instruction decoder (7) to decode instructions; processing circuitry (4) to perform data processing in response to the instructions decoded by the instruction decoder; and memory attribute checking circuitry (16) to check whether a memory access request issued by the processing circuitry satisfies access permissions specified in a plurality of memory attribute entries, each memory attribute entry specifying access permissions for a corresponding address region of variable size within an address space. In response to a range checking instruction specifying address identifying parameters for identifying a first address and a second address, the instruction decoder (7) controls the processing circuitry (4) to set, in at least one software-accessible storage location (12, 13); a status value indicative of whether the first address and the second address correspond to the same memory attribute entry.