Range Code Decompression Circuit for Parallel Bit Decoding

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Solution Overview

Problem

The existing range code decoding process in storage systems is slow due to the inability to perform parallel multiplication and table reference for multiple bits, leading to increased read response times and reduced decompression performance.

Innovation Solution

A decompression circuit that calculates candidate bit values for each bit of an N-bit string based on possible bit histories and selects the correct bit value, allowing for parallel processing and improved decoding speed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If sequential decoding is used for range code, then decoding accuracy is maintained, but decoding speed deteriorates

Engineering Contradiction:
Improvedecoding speedVSAvoidcomplexity of parallel processing
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The decoding process is segmented into multiple independent parallel decoding units, each handling a portion of the input code. Each unit independently calculates candidate bit values and performs selection, enabling parallel processing while maintaining manageable complexity through modular architecture

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Candidate bit values are pre-calculated for multiple possible bit histories before the actual selection process. This preliminary calculation allows the selection unit to quickly choose the correct bit value based on the actual bit history, avoiding sequential computation during the main decoding process

Inventive Principle:
Principle #10Preliminary action

2Productivity

If parallel multiplication is implemented for multiple bits, then processing performance improves, but bit history uncertainty prevents accurate table reference

Engineering Contradiction:
Improveprocessing performanceVSAvoidaccuracy of table reference
Core Design Contradiction:
ProductivityVSMeasurement precision

Solution Approach 1:

Multiple copies of the decoding logic are created, each assuming a different possible bit history. Each copy calculates candidate bit values based on its assumed history, and the selection unit chooses the correct copy's output based on the actual bit history, enabling parallel processing without sacrificing accuracy

Inventive Principle:
Principle #26Copying

Solution Approach 2:

The actual decoded bit history is fed back to the selection unit, which uses this feedback to identify which of the parallel decoding units produced the correct candidate bit values. This feedback mechanism ensures that despite parallel processing with uncertain bit histories, the final output is accurate

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS20240319923A1Apparatus for processing received data
Publication Date: 2024.09.26 HITACHI LTD
  • US20240319923A1 patent drawing
  • US20240319923A1 patent drawing
  • US20240319923A1 patent drawing

AI summary

To speed up decoding of a range code. A decompression circuit calculates a plurality of candidate bit values for each bit of the N-bit string based on a plurality of possible bit histories of a bit before a K-th bit in parallel for a plurality of bits, and repeatedly selects a correct bit value of the K-th bit from the plurality of candidate bit values based on a correct bit history of the bit before the K-th bit to decode the N-bit string.