Hardware Range Detection Logic for Spline Calculation
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Solution Overview
Problem
Existing microprocessor architectures limit the performance of mathematical functions due to serial access to look-up tables and computationally intensive spline calculations, which are resource-consuming and low in performance.
Innovation Solution
Implementing a range detection instruction and corresponding hardware logic to accelerate spline calculations by performing range detection within a spline using binary search techniques, reducing the need for look-up tables and optimizing memory access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If look-up tables are used for mathematical functions in SIMD instructions, then computation accuracy is improved, but memory access time increases due to serial access
Solution Approach 1:
The patent segments the single LUT access operation into multiple parallel access paths by dividing the input operand into high and low parts, allowing simultaneous access to different LUT segments through different memory ports, thereby reducing serial access time while maintaining computation accuracy
Solution Approach 2:
The patent introduces a new dimension of parallelism by utilizing multiple memory ports (port 0 and port 1) to access LUTs simultaneously, transforming the single-threaded serial access model into a multi-dimensional parallel access architecture that reduces memory access time without sacrificing accuracy
2Adaptability or versatility
If spline functions are used for mathematical evaluation, then computational flexibility is improved, but operation complexity increases due to multiple software operations required
Solution Approach 1:
The patent replaces the software-based spline evaluation mechanism with a hardware-accelerated unit that performs range detection, coefficient matching, and polynomial calculation in dedicated circuitry, reducing operation complexity from multiple software steps to a single hardware instruction while preserving computational flexibility
Solution Approach 2:
The patent creates a universal hardware spline evaluation unit that can handle various mathematical functions through a single instruction, making the system adaptable to different computational needs while simplifying the operation interface from multiple software operations to one unified hardware command
3Quantity of substance
If multiple LUT accesses are performed in series for SIMD instructions, then memory resource usage is reduced, but processing speed decreases
Solution Approach 1:
The patent merges multiple sequential LUT access operations into a single parallel execution stage by combining multiple memory ports and access logic into one unified memory subsystem that can service multiple LUTs simultaneously, thereby increasing processing speed while maintaining efficient memory resource utilization
Data Source
AI summary
A technique to accelerate range detection in a spline calcuation. In one embodiment, an instruction and corresponding logic are provided to perform range detection within a computer or processor.