Range Pattern Data Structure for IC Hotspot Identification

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Solution Overview

Problem

Current methods for identifying regions susceptible to fabrication issues in integrated circuit (IC) chips are inefficient due to overestimation of hotspots and failure to incorporate reticle enhancement technology (RET) information, leading to overly conservative routing designs and reduced yield.

Innovation Solution

A data structure called 'range pattern' is used to compactly represent multiple similar patterns in an IC layout, identifying regions prone to fabrication issues by specifying ranges for line segment positions and dimensions, allowing for more accurate identification of hotspot regions and reducing unnecessary corrections.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If current methods are used to identify regions susceptible to fabrication issues, then the identification process is simple, but the accuracy of hotspot identification deteriorates due to overestimation and failure to incorporate RET information

Engineering Contradiction:
Improveaccuracy of hotspot identificationVSAvoidcomplexity of identification method
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent segments the identification process into multiple stages: initial simple pattern matching to identify potential hotspots, followed by RET-aware analysis to filter false positives. The routing correction is also segmented into iterative steps where only regions confirmed as true hotspots are modified. This segmentation allows the system to achieve high accuracy without requiring the entire process to be complex.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces an intermediary RET-aware analysis step between simple hotspot identification and final routing correction. This intermediary layer uses reticle enhancement technology information to verify potential hotspots and eliminate false positives, serving as a mediator that bridges the gap between simple detection and accurate correction without requiring the entire system to be complex.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Loss of time

If simple aerial image simulator is used to find geometric shapes, then the processing time is short, but the ability to factor in RET information is lost leading to overestimation of hotspots

Engineering Contradiction:
Improveprocessing time for hotspot identificationVSAvoidreliability of hotspot identification
Core Design Contradiction:
Loss of timeVSReliability

Solution Approach 1:

The patent performs preliminary action by using the simple aerial image simulator to quickly identify potential hotspots, then follows up with RET-aware analysis only on those specific regions. This preliminary screening approach maintains speed while ensuring reliability, as the complex RET analysis is applied selectively rather than to the entire layout.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent applies partial action by using the computationally intensive RET-aware analysis only on potential hotspot regions identified by the simple simulator, rather than applying it to the entire layout. This partial application of the more complex method achieves reliable identification without the excessive processing time that would result from applying it universally.

Inventive Principle:
Principle #16Partial or excessive action

3Manufacturing precision

If all tagged hotspots are corrected in the layout routing stage, then the routing design becomes more conservative, but the yield is reduced due to overly-conservative design

Engineering Contradiction:
Improveprecision of routing designVSAvoidyield of IC chip production
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

The patent implements feedback by using RET information to verify whether identified hotspots are true fabrication risks before applying corrections. The system continuously refines its hotspot identification based on RET-aware analysis feedback, correcting only those regions that are confirmed as genuine hotspots. This feedback mechanism prevents over-correction and maintains routing design quality without unnecessarily reducing yield.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS8219941B2Range pattern definition of susceptibility of layout regions to fabrication issues
Publication Date: 2012.07.10 SYNOPSYS INC
  • US8219941B2 patent drawing
  • US8219941B2 patent drawing
  • US8219941B2 patent drawing

AI summary

A memory is encoded with a data structure that represents a pattern having a range for one or more dimensions and/or positions of line segments therein. The data structure identifies two or more line segments that are located at a boundary of the pattern. The data structure also includes at least one set of values that identify a maximum limit and a minimum limit (i.e. the range) between which relative location and/or dimension of an additional line segment of the pattern in a portion of a layout of an integrated circuit (IC) chip, represents a defect in the IC chip when fabricated. In most embodiments, multiple ranges are specified in such a range defining pattern for example a width range is specified for the width of a trace of material in the layout and a spacing range is specified for the separation distance between two adjacent traces in the layout.