Range Pattern Matching for IC Layout Hotspot Identification

The patent changes the parameters used for hotspot identification from simple geometric properties to comprehensive lithography simulation results. By incorporating RET information and detailed mask synthesis data, the system transforms the identification criteria to include factors like printed shape fidelity, proximity effects, and fabrication process variations, thereby improving accuracy without sacrificing speed through optimized simulation approaches

The patent replaces the simple aerial image simulator with a more sophisticated lithography simulation system that incorporates RET information. This substitution introduces advanced computational models that account for optical proximity correction, phase shifting mask effects, and sub-resolution assist features, enabling accurate prediction of fabrication outcomes while maintaining computational efficiency through algorithmic optimizations

The patent applies local quality by differentiating between true hotspots and false positives in the layout. By using accurate lithography simulation to identify only the specific regions that will actually print badly, the system applies corrections locally to those areas rather than uniformly across the entire layout. This selective approach maintains routing optimality in non-critical areas while ensuring reliability in problematic regions

The patent avoids excessive correction by identifying and treating only the necessary portion of hotspots. Through improved hotspot identification that factors in RET information, the system determines the minimal set of corrections needed to prevent fabrication failures, rather than applying conservative corrections to all potentially problematic areas, thus maintaining routing design optimality