Range Variable Field Modifiers for High Speed Network Testing
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Solution Overview
Problem
Generating high-speed internet traffic flows to stress test high-speed network components, such as 400 GbE networks, is challenging due to the limitations of conventional RAM resources and bandwidth, which struggle to meet the timing requirements for generating large sets of valid data packets at the necessary speeds.
Innovation Solution
The method involves using range variable field modifiers to generate data packets by storing sets of ranges and pointers in memory, incrementing counters, and modifying packet fields based on corrected pointers and counter values, allowing for the continuous generation of data packets at high speeds through a combination of finite state machine and multi-range variable field modifier feedback loops.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional RAM resources are used to generate large sets of valid ranges of traffic flows, then the network stress testing coverage is improved, but the timing requirements cannot be met due to slow read and update times
Solution Approach 1:
The patent segments the traffic flow generation process into multiple parallel pipelines, each handling a portion of the address space. Instead of using a single RAM resource to generate all flows sequentially, the system divides the work across multiple independent generation units that operate simultaneously, thereby achieving both high coverage and high speed.
Solution Approach 2:
The patent transitions from a single-dimension sequential generation approach to a multi-dimensional parallel architecture. By introducing additional dimensions of parallelism (multiple pipelines, multiple address generators operating simultaneously), the system achieves exponential improvement in packet generation speed while maintaining comprehensive coverage of the address space.
2Loss of time
If RAM read and update operations are performed at maximum frame rate, then packet generation timing is met, but the complexity of the circuitry increases significantly
Solution Approach 1:
The patent pre-generates and stores portions of the address space in parallel before they are needed for packet transmission. By performing address generation in advance and buffering results in parallel memory structures, the system meets strict timing requirements without requiring complex real-time generation circuitry during the critical packet transmission path.
Solution Approach 2:
The patent introduces parallel memory structures and buffer registers as intermediary elements between the address generation logic and the packet transmission interface. These intermediaries decouple the timing-critical transmission path from the address generation process, allowing simpler generation logic to meet stringent timing requirements through pre-computation and parallel buffering.
3Reliability
If the number of flows is increased to stress the network thoroughly, then the testing effectiveness is improved, but the bandwidth requirements exceed available resources
Solution Approach 1:
The patent implements continuous packet generation with no idle cycles between packets. By maintaining uninterrupted flow of test packets through efficient parallel generation and using all available bandwidth resources continuously, the system achieves thorough network stress testing while maximizing the utilization of available bandwidth, thereby reducing the total bandwidth consumption needed for effective testing.
Data Source
AI summary
The disclosed technology teaches techniques for generating a high quantity of internet traffic flows, such as in the form of data packets, to stress test network components by using range variable field modifiers. The techniques generate a large scale of flows at a relatively fast speed by using a process that may involve a finite state machine feedback loop and a multiple range variable field modifier process. Start and end range pointers for range entries of data packet modifiers are stored in memory and used with pointer and counter values, which are varied and updated in a relatively fast feedback loop. Data packet modifiers may be selected based on the pointer and counter values and are used to modify or generate data packets.