Rank-Based Dot Product Circuitry With Shared Partial Product Compression
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional dot product circuitry requires significant circuit area due to high precision computations, exacerbated by increased bit widths and multiplier counts, leading to substantial word growth and power consumption.
Innovation Solution
Group multiplier partial products by their rank and process ones and twos complement bits collectively before combining, reducing compressor word growth and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional dot product circuitry uses separate multiplier groups for each product computation, then each product can be computed accurately, but the circuit area increases significantly
Solution Approach 1:
The patent merges partial products from multiple multipliers into shared compressor groups based on their rank (shift amount). Instead of having separate compressor circuits for each multiplier, partial products with the same rank are combined and processed together, reducing redundant circuitry while maintaining computational accuracy.
Solution Approach 2:
The patent segments the compression process by organizing partial products into distinct rank-based groups (rank 0, rank 1, rank 2, etc.). Each rank group is processed by dedicated compressor circuits, allowing systematic reduction of partial products while minimizing overall circuit area through shared resources.
2Measurement precision
If dot product circuitry increases precision beyond 8 bits, then computation accuracy improves, but circuit area and power consumption increase substantially
Solution Approach 1:
The patent combines partial products of the same rank from multiple high-precision multipliers into shared compressor groups. This merging approach reduces the total number of compressor circuits needed, thereby reducing power consumption while supporting high-precision computations beyond 8 bits.
3Reliability
If dot product circuitry processes sign extension and one's complement bits for each multiplier, then correct signed arithmetic is achieved, but circuit complexity and size increase
Solution Approach 1:
The patent merges sign extension and one's complement processing into the rank-based compression framework. Conversion bits from multiple multipliers are processed together within the shared compressor groups, reducing redundant conversion circuitry while ensuring correct signed arithmetic results.
4Reliability
If conventional circuitry uses separate compressors for each multiplier output, then each multiplier result is processed independently, but the overall circuit size becomes excessive
Solution Approach 1:
The patent merges independent compressor circuits into shared rank-based compressor groups. Partial products from multiple multipliers that share the same rank are processed together by common compressor circuits, reducing the total number of compressors needed while maintaining computation reliability through systematic processing.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
Integrated circuits with dot product circuitry are provided. The dot product circuitry may be configured to generate partial products of different ranks based on the inputs. The partial products may be organized into corresponding groups based on their ranks. Each group of partial products having the same rank can then be compressed using a compressor/reduction tree. At least some of the compressed partial product values may be shifted between the different groups to maintain the proper offset. Each partial product may have an associated one's to two's complement conversion bit. The conversion bits of the various partial product groups can be separately aggregated and then injected into the compressor tree at one or more locations.