Rank-Level DRAM Refresh Control for Lower Refresh Overhead
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Solution Overview
Problem
Existing memory refresh methods in DRAM systems result in inefficient performance due to repeated tests that do not effectively reduce refresh overheads and improve system performance, as the refresh mode selection is not strongly associated with current access request characteristics.
Innovation Solution
A memory refresh method that dynamically adjusts refresh modes based on the distribution of access requests and the proportion of read/write requests, using a buffer queue to manage concurrent access and refresh operations, thereby improving system performance by reducing refresh overheads and enhancing bus utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If repeated refresh tests are performed in different modes to dynamically adjust refresh frequency, then refresh mode adaptability is improved, but system performance is degraded due to test overheads
Solution Approach 1:
The patent applies preliminary action by proactively identifying frozen cycles (periods where memory operations are stalled) and pre-adjusting refresh frequencies before they significantly impact system performance. The memory controller monitors system state and performs refresh mode switching in advance, rather than waiting for performance degradation to occur and then conducting repeated tests to determine the optimal mode.
Solution Approach 2:
The patent implements feedback mechanisms where the memory controller continuously monitors system performance metrics, bus utilization rates, and refresh overheads. Based on this feedback, the controller dynamically adjusts refresh frequencies and modes to optimize system performance while maintaining data integrity in DRAM cells.
2Reliability
If refresh frequency is increased to ensure data retention, then data reliability is improved, but bus utilization rate decreases due to more frequent refresh operations
Solution Approach 1:
The patent applies dynamics by making the refresh frequency adjustable and adaptive rather than fixed. The memory controller dynamically changes refresh frequencies based on current system conditions, bus utilization rates, and data retention requirements. This allows the system to use higher refresh frequencies when needed for data reliability while using lower frequencies when bus utilization is critical, optimizing the trade-off between these two parameters.
Solution Approach 2:
The patent changes the refresh frequency parameter dynamically based on system state. By monitoring bus utilization rates and data retention requirements, the system adjusts the refresh frequency parameter to achieve optimal performance, rather than maintaining a constant refresh rate that would either over-constrain bus utilization or risk data retention.
3Reliability
If refresh operations are performed on all ranks uniformly, then data retention is ensured across all memory, but system performance is degraded due to congestion in the scheduling queue
Solution Approach 1:
The patent applies local quality by treating different memory ranks differently based on their specific needs and current system state. Rather than uniformly refreshing all ranks, the memory controller selectively adjusts refresh frequencies and timing for individual ranks based on local conditions such as access patterns, data retention requirements, and current queue congestion levels. This allows critical ranks to receive appropriate refresh attention while less critical ranks can have reduced refresh overhead.
Solution Approach 2:
The patent segments the refresh operations by rank and time, allowing different refresh strategies to be applied to different memory ranks simultaneously. The memory controller divides the refresh workload across multiple ranks with different timing and frequencies, preventing queue congestion that would occur with uniform simultaneous refresh operations while ensuring each rank receives appropriate refresh attention for data retention.
Data Source
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AI summary
This application provides a memory refresh technology and a computer system. The memory refresh technology is applied to a computer system including a memory controller and a dynamic random access memory DRAM. According to the memory refresh technology, the memory controller receives access requests. The memory controller refreshes a first rank in the plurality of ranks at a T/N interval when a quantity of target ranks of access requests received within a first time period is less than a specified first threshold and a proportion of read requests or write requests in the access requests is greater than a specified second threshold. T is used to indicate a standard average refresh interval, and N is an integer greater than 1. The memory refresh technology provided in this application can improve performance of the computer system in a memory refresh process.