Partially Parallel Rank Order Filter for FPGA Resource Scaling
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Solution Overview
Problem
Existing rank order filters for image and video processing face limitations in scalability and resource utilization, particularly when transitioning from one-dimensional to two-dimensional filters, leading to inefficiencies in processing speed and resource management in programmable logic devices like FPGAs.
Innovation Solution
A scalable architecture for rank order filtering is implemented, utilizing a filter core with multiple stages of registers and comparison blocks, along with a delay line and conversion stage, to process multiple input samples in parallel, allowing for a partially parallel or hybrid implementation that optimizes clock frequency and resource usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a fully parallel implementation of rank order filter is used, then processing speed is improved, but resource consumption increases excessively
Solution Approach 1:
The filter core is divided into multiple stages (first stage registers, comparator stage, second stage registers, third stage registers, conversion stage) that process data in a pipelined manner. This segmentation allows the system to achieve high throughput without requiring all resources to operate in full parallel simultaneously, thus improving processing speed while controlling resource consumption.
Solution Approach 2:
The architecture uses dynamic data flow through the pipeline stages, where data moves through different processing phases at different clock cycles. The partial parallelism is achieved by having multiple data elements progress through different stages simultaneously, optimizing the balance between processing speed and resource utilization based on the actual data flow requirements.
2Quantity of substance
If a word serial instantiation of rank order filter is used, then resource consumption is reduced, but operating frequency becomes insufficient for required processing rates
Solution Approach 1:
The pipeline architecture enables dynamic operation where the filter core can operate at high clock frequencies by processing multiple samples through different stages in parallel. Each stage can be optimized for speed while the overall system achieves high throughput through the pipelined data flow, allowing operation at frequencies sufficient for high-speed image and video processing applications.
3Device complexity
If conventional rank order filter architecture is used, then implementation is simpler, but scalability to two-dimensional filters is limited
Solution Approach 1:
The filter core architecture is designed as a universal platform that can be configured for different filter sizes and dimensions. The staged pipeline structure with configurable register widths and comparator logic allows the same basic architecture to be scaled from one-dimensional to two-dimensional filters, and adapted to different window sizes, without requiring complete redesign. This multi-functionality achieves scalability while maintaining reasonable implementation complexity.
Data Source
AI summary
A rank order filter and instantiation thereof in programmable logic is described. A maximum filter core frequency is determined for an input sampling frequency, a filter window height, and a number of input samples. The maximum filter core frequency is greater than the sampling frequency. The maximum filter core frequency may be insufficient for a word serial instantiation of the rank order filter in the programmable logic. The size of a fully parallel instantiation of the rank order filter may be excessive in programmable logic. Thus, a partially parallel filter core is instantiated for the rank order filter with overclocking.