RANS Decoding Architecture With Two-Phase Adaptive Symbol Handling
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Solution Overview
Problem
Existing RANS encoding/decoding technologies face challenges in computational efficiency and adaptiveness to different distributions or patterns of symbol values, limiting their effectiveness in media compression.
Innovation Solution
Implementing RANS encoding/decoding operations in two phases using special-purpose hardware, adapting symbol width, probability models, and selectively flushing or retaining decoder states on a fragment-by-fragment basis to improve computational efficiency and compression efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If RANS encoding/decoding is implemented using general-purpose processors, then flexibility and ease of implementation are improved, but computational efficiency and processing speed deteriorate
Solution Approach 1:
The patent replaces general-purpose processor implementations with dedicated hardware circuitry specifically designed for RANS encoding and decoding operations. This substitution of mechanical/computational systems with specialized hardware architecture achieves both high computational efficiency and simplified implementation by integrating all required operations into a unified hardware structure.
Solution Approach 2:
The patent divides the RANS encoding/decoding process into distinct functional modules including state normalization units, output computation units, and state evolution units. Each module is implemented as separate hardware components that can operate independently and concurrently, improving overall computational efficiency while maintaining implementation clarity.
2Device complexity
If RANS decoding uses a single-phase architecture, then device complexity is reduced, but computational efficiency and throughput deteriorate
Solution Approach 1:
The patent implements a two-phase RANS decoding architecture where Phase 1 handles state normalization and Phase 2 handles output computation and state evolution. This segmentation of the decoding process into distinct phases allows for optimized resource utilization and concurrent operation, significantly improving computational efficiency and throughput compared to single-phase architectures.
Solution Approach 2:
The patent employs periodic alternating execution of Phase 1 and Phase 2 operations in a pipelined manner. While Phase 1 processes one symbol, Phase 2 can simultaneously process previous symbols, creating a periodic rhythm of operations that maximizes hardware utilization and improves overall decoding throughput.
3Device complexity
If RANS encoding/decoding uses fixed symbol width, then device complexity is reduced, but adaptability to different symbol distributions deteriorates
Solution Approach 1:
The patent implements dynamic symbol width adjustment capability in the RANS encoder and decoder, allowing the symbol width to be changed based on the statistical characteristics of the input data. The system can adaptively select from multiple symbol width configurations (e.g., 8-bit, 16-bit, 32-bit) to optimize compression performance for different symbol distributions while maintaining a unified hardware architecture that supports all configurations.
Solution Approach 2:
The patent enables change of key parameters including symbol width, probability distribution models, and state representation formats to match the characteristics of different input data. By allowing these parameters to be dynamically adjusted based on data analysis, the system achieves high adaptability to various symbol distributions without requiring completely different hardware designs for each case.
4Productivity
If RANS decoder state is retained across all fragments, then compression efficiency is improved, but adaptability to different data patterns deteriorates
Solution Approach 1:
The patent implements dynamic state management where the decoder can selectively retain or flush its internal state based on the characteristics of incoming data fragments. The system analyzes data patterns and dynamically decides whether to maintain continuity of the decoder state for compression efficiency or to flush and reinitialize the state for better adaptability to new data patterns, providing flexible adaptation to different data scenarios.
Solution Approach 2:
The patent employs periodic flushing of the decoder state at designated fragment boundaries or based on data pattern detection. This periodic state reset allows the system to adapt to changing data distributions while maintaining compression efficiency within each fragment, creating a rhythm of state retention and flushing that balances both compression performance and adaptability.
Data Source
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AI summary
Innovations in range asymmetric number system ("RANS") coding and decoding are described herein. Some of the innovations relate to hardware implementations of RANS decoding that organize operations in two phases, which can improve the computational efficiency of RANS decoding. Other innovations relate to adapting RANS encoding/decoding for different distributions or patterns of values for symbols. For example, RANS encoding/decoding can adapt by switching a default symbol width (the number of bits per symbol), adjusting symbol width on a fragment-by-fragment basis for different fragments of symbols, switching between different static probability models on a fragment-by-fragment basis for different fragments of symbols, and/or selectively flushing (or retaining) the state of a RANS decoder on a fragment-by-fragment basis for different fragments of symbols. In many cases, such innovations can improve compression efficiency while also providing computationally efficient performance.