RANS Decoding with Two-Phase Hardware and Fragment Model Switching
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Solution Overview
Problem
Current Range Asymmetric Number System (RANS) encoding/decoding approaches face limitations in computational efficiency and adaptiveness, particularly in hardware implementations and handling varying distributions of symbol values.
Innovation Solution
The implementation of a two-phase RANS decoding structure, adaptable symbol widths, switchable static probability models, selective flushing of decoder state, and fragment-by-fragment adjustments to improve compression efficiency and computational performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional RANS decoding is implemented in hardware, then compression efficiency is improved, but computational complexity increases
Solution Approach 1:
The RANS decoding process is divided into two distinct phases: Phase 0 performs state updates using probability information from previous iterations, while Phase 1 performs merging of encoded data and generation of output symbols. This segmentation allows each phase to be optimized independently in hardware, reducing overall computational complexity while maintaining compression efficiency.
Solution Approach 2:
The patent introduces dynamic adaptability by allowing switching between different static probability models on a fragment-by-fragment basis, and by enabling selective flushing of decoder state. This dynamic behavior allows the hardware to adapt to varying symbol distributions without requiring complex real-time probability estimation, thus maintaining efficiency while managing computational load.
2Adaptability or versatility
If RANS encoding/decoding uses fixed symbol width, then device complexity is reduced, but adaptability to different symbol distributions decreases
Solution Approach 1:
The patent enables dynamic adjustment of symbol width on a fragment-by-fragment basis. The encoder can select different symbol widths (e.g., 8-bit, 16-bit, 32-bit) depending on the characteristics of each fragment, allowing adaptation to different symbol distributions without requiring a single complex variable-width implementation throughout the entire system.
Solution Approach 2:
By changing the symbol width parameter between fragments rather than within a fragment, the system achieves adaptability to different data characteristics while maintaining simpler hardware implementation. Each fragment can be processed with an optimized fixed symbol width, avoiding the complexity of dynamic width adjustment during active decoding.
3Speed
If RANS decoding processes entire bitstreams continuously, then processing speed is improved, but memory requirements and state management complexity increase
Solution Approach 1:
The bitstream is divided into fragments that can be processed independently. Each fragment can be decoded with its own initial state, and the decoder can selectively flush state between fragments. This segmentation reduces memory requirements compared to maintaining state for the entire bitstream, while still allowing efficient processing through parallel fragment decoding.
Solution Approach 2:
The patent implements selective flushing of decoder state between fragments. When a fragment is decoded, the state can be discarded (flushed) rather than maintained, reducing memory requirements. The ability to recover initial state information for each fragment allows independent processing without requiring continuous state management across the entire bitstream.
Data Source
AI summary
Innovations in range asymmetric number system (“RANS”) coding and decoding are described herein. Some of the innovations relate to hardware implementations of RANS decoding that organize operations in two phases, which can improve the computational efficiency of RANS decoding. Other innovations relate to adapting RANS encoding/decoding for different distributions or patterns of values for symbols. For example, RANS encoding/decoding can adapt by switching a default symbol width (the number of bits per symbol), adjusting symbol width on a fragment-by-fragment basis for different fragments of symbols, switching between different static probability models on a fragment-by-fragment basis for different fragments of symbols, and/or selectively flushing (or retaining) the state of a RANS decoder on a fragment-by-fragment basis for different fragments of symbols. In many cases, such innovations can improve compression efficiency while also providing computationally efficient performance.


