Rapid Expression Coverage for Circuit Design Verification

Solution Overview

Problem

Current design verification tools face inefficiencies in performing functional verification due to the exponential increase in input vectors for expression coverage, leading to long processing times and large memory requirements when generating truth-tables for circuit designs.

Innovation Solution

The implementation of a rapid expression coverage process that divides expressions into sub-expressions, allowing for separate evaluation during simulation to detect coverage events, thereby eliminating the need to generate complete truth-tables for each possible input vector.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If complete truth-tables are generated for each possible input vector to ensure expression coverage, then measurement precision is improved, but loss of time and use of energy worsen due to exponential increase in processing requirements

Engineering Contradiction:

Improveexpression coverage accuracyVSAvoidprocessing time

Core Design Contradiction:

Measurement precisionVSLoss of time

Solution Approach 1:

The patent segments the expression coverage problem by dividing the set of all possible input vectors into multiple groups, where each group is associated with a different subset of inputs to the expression. This allows the verification tool to evaluate coverage for each input vector independently within its group, rather than generating and processing complete truth-tables for all possible input combinations, thereby reducing processing time while maintaining coverage accuracy.

Inventive Principle:

Principle #1Segmentation

2Measurement precision

If complete truth-tables are generated for each possible input vector to ensure expression coverage, then measurement precision is improved, but use of energy worsens due to large memory requirements

Engineering Contradiction:

Improveexpression coverage accuracyVSAvoidmemory requirements

Core Design Contradiction:

Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The patent segments the expression coverage problem by dividing the set of all possible input vectors into multiple groups, where each group is associated with a different subset of inputs to the expression. This allows the verification tool to evaluate coverage for each input vector independently within its group, rather than generating and processing complete truth-tables for all possible input combinations, thereby reducing processing time while maintaining coverage accuracy.

Inventive Principle:

Principle #1Segmentation

3Reliability

If exhaustive truth-table generation is performed to achieve complete expression coverage, then reliability is improved, but productivity worsens due to long processing times

Engineering Contradiction:

Improvefunctional verification reliabilityVSAvoidverification throughput

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The patent segments the expression coverage problem by dividing the set of all possible input vectors into multiple groups, where each group is associated with a different subset of inputs to the expression. This allows the verification tool to evaluate coverage for each input vector independently within its group, rather than generating and processing complete truth-tables for all possible input combinations, thereby reducing processing time while maintaining coverage accuracy.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent applies partial action by evaluating only the necessary subset of input vectors for each expression based on its specific input requirements, rather than performing exhaustive evaluation of all possible input vectors. This partial evaluation approach maintains sufficient coverage reliability while significantly improving verification productivity.

Inventive Principle:

Principle #16Partial or excessive action

Data Source

PatentUS8978002B1Rapid expression coverage

Publication Date: 2015.03.10 SIEMENS INDUSTRY SOFTWARE INC

AI summary

This application discloses simulating a circuit design with a test bench and determining an expression coverage in the circuit design by the test bench with a rapid expression coverage process. The rapid expression coverage process can include dividing an expression in the circuit design into multiple sub-expressions, and separately evaluating each of the multiple sub-expressions during simulation of the circuit design to detect whether first operands in the corresponding sub-expressions receive each available input state, while second operands in the corresponding sub-expressions are in a non-masking state. The rapid expression coverage can generate an expression coverage metric to indicate whether expressions in the circuit design were covered by the test bench during the simulation of the circuit, for example, without having to generate truth-tables that include each possible input vector for each expression.