Rare Earth Aluminate Interfacial Layer for III-V MOS Leakage
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Solution Overview
Problem
In III-V MOS devices, reducing equivalent oxide thickness leads to increased tunnelling leakage current and decreased charge mobility, and existing solutions with high-k dielectrics often result in high defect densities and large equivalent oxide thickness.
Innovation Solution
A semiconductor structure with a III-V substrate and a high-k interfacial layer comprising rare earth aluminate, which reduces interface defect density and allows for a low leakage current while maintaining good charge mobility, achieved by using a rare earth aluminate as the interfacial layer and a high-k dielectric layer with a high dielectric constant.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the equivalent oxide thickness is lowered to achieve miniaturization, then the device size is reduced, but the tunnelling leakage current increases
Solution Approach 1:
The patent employs a composite gate dielectric structure consisting of a high-k dielectric layer (such as HfO2, TiO2, or Ta2O5) combined with an interfacial layer (such as SiO2 or SiNx). This composite structure leverages the high dielectric constant of the high-k material to achieve low equivalent oxide thickness while the interfacial layer provides a large conduction band offset to suppress tunnelling leakage current, thus resolving the contradiction between miniaturization and leakage current reduction.
Solution Approach 2:
The patent applies different material properties to different regions of the gate dielectric: the interfacial layer near the semiconductor substrate is designed with high bandgap and large conduction band offset to minimize leakage, while the bulk high-k dielectric layer provides high capacitance. This local differentiation of material quality allows simultaneous achievement of low equivalent oxide thickness and low tunnelling leakage current.
2Power
If high-k dielectrics are used to reduce equivalent oxide thickness, then the capacitance is improved, but the tunnelling leakage current increases due to small bandgap
Solution Approach 1:
The patent combines high-k dielectric materials (providing high capacitance) with interfacial layer materials having large conduction band offsets (suppressing leakage). The high-k dielectric layer contributes to high capacitance through its high dielectric constant, while the interfacial layer prevents tunnelling leakage through its large band offset, thus resolving the contradiction between capacitance improvement and leakage current reduction.
Solution Approach 2:
The gate dielectric is structured with an interfacial layer optimized for leakage suppression (large conduction band offset) adjacent to the substrate, and a high-k dielectric layer optimized for capacitance in the bulk region. This local quality differentiation allows the system to simultaneously achieve high capacitance and low tunnelling leakage current despite the small bandgap of high-k materials.
3Object-generated harmful factors
If multiple layers are inserted between substrate and dielectric to reduce leakage, then the leakage current is reduced, but the device complexity increases
Solution Approach 1:
The patent uses a composite gate dielectric structure with typically two main layers: an interfacial layer and a high-k dielectric layer. This composite approach reduces leakage current effectively while maintaining relatively simple fabrication processes and layer counts, avoiding the complexity multiplication that would result from inserting multiple separate functional layers.
Solution Approach 2:
The interfacial layer in the patent serves multiple functions simultaneously: it provides a large conduction band offset to suppress leakage current, acts as a buffer to reduce interface defects, and maintains good charge mobility in the underlying III-V substrate. This multi-functionality of a single layer type reduces the need for multiple separate layers, thereby limiting device complexity while achieving leakage reduction.
4Length of moving object
If the equivalent oxide thickness is reduced, then the device is miniaturized, but the charge mobility in the III-V substrate decreases
Solution Approach 1:
The patent employs a composite gate dielectric structure where the high-k dielectric layer provides high capacitance with minimal thickness, and the interfacial layer provides a large conduction band offset. This combination enables strong electric field control (improving charge mobility) while maintaining low equivalent oxide thickness, thus resolving the contradiction between miniaturization and charge mobility preservation in III-V substrates.
Solution Approach 2:
The gate dielectric structure is designed with an interfacial layer that creates a large conduction band offset locally at the substrate interface, which prevents carrier scattering and maintains high charge mobility in the III-V substrate. Simultaneously, the overall equivalent oxide thickness is kept low through the use of high-k dielectric material in the bulk region, thus resolving the contradiction between miniaturization and charge mobility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves a low leakage current, high charge mobility, and small equivalent oxide thickness, improving the performance of III-V MOS devices by reducing interface defects and enhancing capacitance.
Implementation Method 1
A low defect density at an interface between the semiconductor substrate and the dielectric, thereby permitting a good mobility in a region of the semiconductor substrate
Implementation Method 2
a high dielectric constant for the interfacial layer or for a stack interfacial layer/high-k dielectric layer, thereby permitting a good capacitance and a low leakage current
Implementation Method 3
when the equivalent oxide thickness is lowered, the tunnelling leakage current through the dielectric tends to get higher
Data Source
AI summary
A semiconductor structure comprises a substrate including a III-V material, and a high-k interfacial layer overlaying the substrate. The interfacial layer includes a rare earth aluminate. The present disclosure also relates to an n-type FET device comprising the same, and a method for manufacturing the same.