Rare-Earth Interfacial Layer for Low-CET Gate Insulation
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Solution Overview
Problem
The challenge in semiconductor technology is to reduce the capacitance equivalent thickness (CET) of the insulating portion in transistors while maintaining sufficient physical thickness, to enhance operating performance and reduce gate leakage current.
Innovation Solution
The introduction of an interfacial layer with a high dielectric constant, made from rare-earth metal silicates, and a barrier layer with high band gap energy, which are formed between the channel and the gate dielectric layer, helps in achieving a reduced CET value and minimizing gate leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the physical thickness of the insulating portion is reduced to lower CET, then the operating performance is improved, but the gate leakage current increases
Solution Approach 1:
The insulating portion is segmented into multiple functional layers: an interfacial layer (first insulating layer) and a gate dielectric layer (second insulating layer). The interfacial layer provides a thin physical structure to reduce CET, while the gate dielectric layer provides sufficient thickness to prevent gate leakage, resolving the contradiction between performance and leakage control.
Solution Approach 2:
The patent uses composite material structures with different dielectric constants. The interfacial layer has a first dielectric constant while the gate dielectric layer has a second dielectric constant. This composite structure allows the system to achieve low CET through the thin interfacial layer while maintaining leakage prevention through the thicker gate dielectric layer with appropriate dielectric properties.
2Reliability
If the CET of the insulating portion is reduced, then the transistor performance is enhanced, but the physical thickness becomes insufficient
Solution Approach 1:
The insulating portion is divided into two distinct layers with different functions. The interfacial layer is designed with minimal thickness to contribute minimally to CET, while the gate dielectric layer provides the necessary physical thickness. This segmentation allows the total CET to be reduced while maintaining sufficient overall physical thickness for device reliability.
Solution Approach 2:
Different regions of the insulating portion are assigned different properties. The interfacial layer near the channel interface is made thin with specific dielectric properties to minimize CET contribution, while the gate dielectric layer is made thicker with appropriate dielectric constant to provide sufficient physical barrier. This local differentiation resolves the contradiction between CET reduction and thickness maintenance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in improved saturation drain current and reduced gate leakage current, thereby enhancing the overall performance of the transistor.
Implementation Method 1
an interfacial layer with a high dielectric constant, made from rare-earth metal silicates
Implementation Method 2
a barrier layer with high band gap energy, which are formed between the channel and the gate dielectric layer
Data Source
AI summary
A method for manufacturing a semiconductor device includes: forming a channel portion which includes a semiconductor material; sequentially forming a first oxide film and a second oxide film on the channel portion, the first oxide film and the second oxide film being made of different materials, one of the first oxide film and the second oxide film including a rare-earth metal; performing a treatment such that the first oxide film and the second oxide film are formed into an interfacial layer which includes a first dielectric material and which is formed on the channel portion; forming a gate dielectric layer which includes a second dielectric material and which is formed on the interfacial layer, the second dielectric material being different from the first dielectric material; and forming a gate electrode on the gate dielectric layer.