Rare Earth Oxide Isolation in Stacked Vertical Transistors
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Solution Overview
Problem
Conventional vertical field-effect transistors (VFETs) face challenges in increasing transistor density per unit chip area while maintaining sufficient isolation between n-type and p-type devices, leading to inefficient use of device footprint and increased middle of the line (MOL) resistance.
Innovation Solution
The use of a rare earth oxide (REO) isolation layer between vertically stacked n-type and p-type transistors, enabling robust isolation and reducing device footprint by allowing for closer packing of transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional VFET structures with side-by-side n-type and p-type transistors are used, then device isolation is maintained, but device footprint area increases and transistor density decreases
Solution Approach 1:
The patent transitions from a planar side-by-side arrangement to a vertical stacked configuration, utilizing the third dimension (vertical direction) to increase transistor density. Multiple transistors are stacked vertically with source/drain regions positioned at different heights, allowing closer packing without compromising isolation.
Solution Approach 2:
The patent implements nested source/drain regions where upper source/drain regions are positioned above and nested relative to lower source/drain regions. This nesting approach allows multiple transistors to occupy overlapping horizontal footprints while maintaining vertical separation through the isolation layer.
2Area of stationary object
If transistor stacking is implemented to increase density, then device footprint is reduced, but isolation between n-type and p-type devices becomes challenging
Solution Approach 1:
The patent introduces a rare earth oxide isolation layer as an intermediary material positioned between upper and lower source/drain regions. This isolation layer acts as a mediator that provides electrical isolation between stacked transistors of different types (n-type and p-type), enabling vertical stacking while maintaining proper device isolation and preventing unwanted electrical interactions.
3Quantity of substance
If closer packing of transistors is achieved through stacking, then transistor density increases, but middle of the line resistance increases
Solution Approach 1:
The patent moves current flow from a purely lateral path to a vertical path through the stacked structure. By utilizing the vertical dimension for current transport between source and drain regions, the design reduces the lateral current path length, thereby reducing middle of the line resistance while achieving higher density through vertical stacking.
Data Source
AI summary
A method for manufacturing a semiconductor device includes forming a first vertical transistor on a semiconductor substrate, and forming a second vertical transistor stacked on the first vertical transistor. In the method, an isolation layer is formed between the first and second vertical transistors. The isolation layer includes a rare earth oxide.