RAS State Machine for CPU Error Handling
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Solution Overview
Problem
Current computing systems rely on BIOS SMM to handle RAS events, which can lead to system-wide interruptions and inefficiencies, particularly in multicore processors, where only affected cores should be halted for error handling, but all cores are often quiesced, causing delays and performance losses.
Innovation Solution
Implementing a dedicated RAS state machine (RAS_SM) in hardware that communicates with the management infrastructure and OS, allowing only affected cores to be halted and enabling independent error handling, reducing dependence on BIOS for system recovery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If BIOS SMM is used to handle RAS events, then system-wide error handling is achieved, but all processor cores are halted causing system performance loss
Solution Approach 1:
The patent divides the error handling responsibility from the unified BIOS SMM approach into separate, dedicated RAS state machines for different error types (machine check errors, performance monitoring errors, thermal errors). Each RAS_SM handles specific error conditions independently, allowing only affected cores to be halted rather than all cores, thus resolving the contradiction between reliable error handling and system performance maintenance.
2Reliability
If BIOS SMM handles all RAS events, then comprehensive error coverage is achieved, but system complexity and OS burden increase
Solution Approach 1:
The patent extracts the RAS event handling function from the BIOS SMM and implements it in dedicated hardware RAS state machines within the processor. This extraction reduces the complexity of the BIOS and operating system by moving error handling logic into the processor itself, while maintaining comprehensive error coverage through multiple specialized RAS_SM units that monitor different error conditions independently.
3Stability of the object's composition
If all cores are quiesced for error handling, then system stability is ensured, but interruption time and recovery delay increase
Solution Approach 1:
The patent applies local quality by having each RAS state machine handle errors locally and independently, quiescing only the specific processor core or functional unit that generated the error rather than all cores. This localized error handling maintains system stability in the affected area while allowing other parts of the system to continue operating, thereby reducing overall interruption time and recovery delay.
Data Source
AI summary
Systems and methods for an integrated reliability, availability, and serviceability (RAS) state machine are provided. Handling of RAS events by the Basic Input Output System (BIOS) of an integrated circuit device can result in lost processing time on the processing cores of a multi-core processor resulting from numerous system management interrupts generated by the BIOS. To reduce lost processing time, a dedicated state machine can execute instructions to handle RAS events independently of the BIOS and minimize the number of system management interrupts.