Raster-to-Block Converter Using Modular Address Mapping
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Solution Overview
Problem
Current systems for converting digital images from raster order to block order require significant memory and are complex to implement, especially in video applications where memory is high-performance and expensive, and existing solutions either use dual buffers at twice the memory cost or are complicated and not scalable.
Innovation Solution
A reordering converter using a single image band buffer with modular arithmetic for address conversion, allowing efficient conversion between raster and block orders, reducing memory requirements and simplifying implementation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If dual buffers are used for raster to block conversion, then conversion capability is achieved, but memory cost doubles
Solution Approach 1:
The patent merges the functions of two separate buffers into a single buffer by implementing a ping-pong buffering mechanism where the same physical memory is alternately used for writing and reading operations. This combining approach maintains the conversion capability while halving the memory requirements from dual buffers to a single buffer.
Solution Approach 2:
The patent employs periodic action through the ping-pong buffering mechanism, where the buffer roles (read/write) are periodically swapped after each image band processing cycle. This periodic switching allows the same memory to be reused in alternating cycles, enabling efficient memory utilization with reduced memory cost while maintaining continuous conversion operation.
2Adaptability or versatility
If complex conversion systems are implemented, then conversion functionality is achieved, but implementation complexity increases
Solution Approach 1:
The patent implements a universal converter design that can perform both raster-to-block and block-to-raster conversions using the same hardware architecture and single buffer. The address generator and control logic are designed to handle both conversion directions, eliminating the need for separate dedicated converters and reducing overall system complexity.
Solution Approach 2:
The patent introduces dynamic elements through the ping-pong buffering mechanism and configurable address generation, allowing the system to adapt its operation mode (read/write roles) based on the conversion direction and image band processing stage. This dynamic switching capability enables a single static hardware design to perform multiple conversion functions with reduced complexity.
3Speed
If high-performance memory is used for video applications, then processing speed is improved, but cost increases
Solution Approach 1:
The patent creates a logical copy of the buffer functionality through the ping-pong mechanism, where the same physical memory serves two logical buffer roles at different times. This allows the system to achieve the functional equivalent of dual high-performance buffers while using only one physical high-performance memory module, thereby maintaining processing speed while reducing memory cost.
Data Source
AI summary
A raster to block converter and equivalently a block to raster converter can be implemented using enough memory to contain a single image band, that is a band of pixels of height equal to a single block but spanning the entire width of an image. The raster to block converter can operate at full rate so that as soon as a pixel is read out from the memory a new pixel can be stored in its place. The location of a pixel can be tracked using a mapping involving basic modular arithmetic. This raster to block converter is scalable so that it can work with any size image and block size.