Neural Parasitic Modeling for Rasterized IC Wire Structures
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing techniques struggle to accurately model parasitic capacitance, resistance, and inductance in semiconductor designs, especially at smaller process geometries, due to increasing manufacturing process variations and complex geometries, impacting circuit delay, energy consumption, and reliability.
Innovation Solution
A method utilizing a neural network to rasterize wire structures into pixel-based definitions, generating parasitic parameters by training on curvilinear and rectilinear shapes, incorporating manufacturing process information, and using field solvers to calculate parasitic effects, leveraging GPU and TPU architectures for efficient computation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional parasitic extraction techniques are used, then the process is simpler and faster, but the accuracy of parasitic modeling deteriorates at smaller process geometries
Solution Approach 1:
The wire structure is decomposed into multiple segments, with each segment's parasitic effects calculated independently by the neural network. This segmentation allows the complex extraction problem to be broken down into manageable parts while maintaining high accuracy for each segment, resolving the contradiction between accuracy and complexity.
Solution Approach 2:
The patent uses rasterization to create a pixel-based copy of the wire structure geometry, which serves as input to the neural network. This copied representation simplifies the geometric data while preserving essential spatial relationships, enabling accurate parasitic calculation without requiring complex geometric processing.
2Measurement precision
If detailed parasitic extraction is performed to improve accuracy, then the computational time increases
Solution Approach 1:
The neural network is pre-trained on a comprehensive dataset of wire structures and their corresponding parasitic values. This preliminary training phase allows the network to learn complex parasitic relationships in advance, so that during actual extraction, accurate results are obtained rapidly without requiring time-consuming iterative calculations.
Solution Approach 2:
The patent replaces traditional field solver methods (which require solving complex electromagnetic equations) with a neural network-based system. This substitution transitions from a computationally intensive physics-based approach to a data-driven machine learning approach, dramatically reducing computation time while maintaining or improving accuracy.
3Reliability
If manufacturing process variations are accounted for to improve reliability, then the modeling complexity increases
Solution Approach 1:
The patent incorporates manufacturing process variations by training the neural network on data that includes local geometric variations and process-specific parameters. Each wire structure's parasitic effects are calculated with local quality considerations, accounting for variations in wire dimensions, spacing, and material properties that occur during manufacturing, thereby improving reliability without requiring a completely complex modeling framework.
Data Source
AI summary
Some embodiments provide a method for calculating parasitic parameters for a pattern to be manufactured on an integrated circuit (IC) substrate. The method receives a definition of a wire structure as input. The method rasterizes the wire structure (e.g., produces pixel-based definition of the wire structure) to produce several images. Before rasterizing the wire structure, the method in some embodiments decomposes the wire structure into several components (e.g., several wires, wire segments or wire structure portions), which it then individually rasterizes. The method then uses the images as inputs to a neural network, which then calculates parasitic parameters associated with the wire structure. In some embodiments, the parasitic parameters include unwanted parasitic capacitance effects exerted on the wire structure. Conjunctively, or alternatively, these parameters include unwanted parasitic resistance and/or inductance effects on the wire structure.