Rasterized Wire Modeling for Accurate IC Parasitic Extraction
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Solution Overview
Problem
Existing techniques struggle to accurately model parasitic capacitance, resistance, and inductance in semiconductor manufacturing at smaller process geometries due to increasing manufacturing process variations and complex geometries, impacting circuit delay, energy consumption, and reliability.
Innovation Solution
A method using neural networks to rasterize wire structures into pixel-based images, training these networks to calculate parasitic parameters, and utilizing GPU or TPU devices for efficient capacitance extraction, replacing traditional CPU-based methods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional CPU-based methods are used for parasitic extraction, then the process is simpler to implement, but the computation speed is slow and accuracy is insufficient for complex geometries
Solution Approach 1:
The patent replaces traditional CPU-based numerical computation methods with GPU/TPU-based parallel computing architecture. The parasitic extraction algorithm is transformed to utilize the massively parallel processing capabilities of graphics processing units and tensor processing units, substituting the sequential mechanical computation approach with a parallel hardware-accelerated approach that achieves both higher accuracy and faster computation speeds
Solution Approach 2:
The patent transitions from 2D wire structure representations to 3D volumetric modeling for parasitic extraction. By incorporating vertical dimension information and creating three-dimensional models of interconnect structures, the system captures more accurate electromagnetic field interactions and parasitic effects that cannot be represented in two dimensions, thereby improving measurement precision
2Reliability
If manufacturing process variations are accounted for in parasitic modeling, then the reliability improves, but the complexity of the modeling process increases
Solution Approach 1:
The patent performs preliminary characterization of manufacturing process variations by creating multiple process corner models (e.g., slow-slow, fast-fast, typical-typical) before actual parasitic extraction. These pre-defined process variation models are then applied during extraction to account for manufacturing variations, allowing reliability assessment without adding excessive complexity to the core extraction algorithm
Solution Approach 2:
The patent systematically varies key geometric and material parameters (wire width, spacing, dielectric constants, conductor thickness) to model manufacturing process variations. By changing these parameters across defined ranges and extracting parasitics for each variation case, the system captures the impact of manufacturing tolerances on circuit reliability while maintaining a structured approach that manages modeling complexity
3Manufacturing precision
If curvilinear shapes are used to represent wire structures, then the manufacturing precision improves, but the computational complexity increases
Solution Approach 1:
The patent explicitly models wire structures with curvilinear (curved) geometries rather than simplified straight-line approximations. By using actual curvilinear shapes that match manufactured features, the system achieves higher manufacturing precision in parasitic modeling, accurately capturing electromagnetic field distributions around rounded corners and curved interconnect paths
Solution Approach 2:
The patent divides complex curvilinear wire structures into smaller manageable segments or sections for processing. Each segment is modeled with appropriate geometric detail, and the overall parasitic parameters are computed by combining segment contributions. This segmentation approach maintains manufacturing precision for complex geometries while reducing computational complexity through divide-and-conquer strategy
Data Source
AI summary
Some embodiments provide a method for calculating parasitic parameters for a pattern to be manufactured on an integrated circuit (IC) substrate. The method receives a definition of a wire structure as input. The method rasterizes the wire structure (e.g., produces pixel-based definition of the wire structure) to produce several images. Before rasterizing the wire structure, the method in some embodiments decomposes the wire structure into several components (e.g., several wires, wire segments or wire structure portions), which it then individually rasterizes. The method then uses the images as inputs to a neural network, which then calculates parasitic parameters associated with the wire structure. In some embodiments, the parasitic parameters include unwanted parasitic capacitance effects exerted on the wire structure. Conjunctively, or alternatively, these parameters include unwanted parasitic resistance and/or inductance effects on the wire structure.