Rate-Changeable Clock Synchronization Without Blockout Periods
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Solution Overview
Problem
In time-triggered systems, existing clock synchronization methods face challenges in simultaneously adjusting clock rate and state due to the need for separate adjustments, leading to a 'blockout period where both cannot be made simultaneously, affecting the precision and efficiency of clock synchronization.
Innovation Solution
Implementing a rate-changeable clock that allows for simultaneous clock-rate and clock-state adjustments using relative measurements, enabling the generation of a second clock signal for determining transmission start times and making adjustments without a blockout period.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If virtual-clock offset adjustment is made for clock-state correction, then clock-state synchronization is improved, but clock-rate correction cannot be simultaneously made creating a blockout period
Solution Approach 1:
The patent segments the clock adjustment function into two independent parts: a virtual clock for state correction and a hardware clock for rate correction. This segmentation allows both corrections to operate simultaneously without interference, eliminating the blockout period while maintaining synchronization precision.
Solution Approach 2:
The virtual clock acts as an intermediary mechanism that handles clock-state correction independently from the hardware clock. By using the virtual clock as a mediator for state adjustments, the system can perform both state and rate corrections concurrently without blocking either function.
2Device complexity
If hardware clock rate is fixed, then device complexity is reduced, but clock-rate correction cannot be applied simultaneously with clock-state correction
Solution Approach 1:
The patent divides the clock system into a fixed hardware clock (for rate correction) and a virtual clock (for state correction). This segmentation allows the hardware clock to remain simple and fixed while still achieving reliable synchronization through the coordinated action of both clocks.
Solution Approach 2:
The virtual clock is essentially a copy or software implementation of the hardware clock that can be adjusted independently. This copying allows the system to maintain a simple hardware clock while achieving comprehensive synchronization capabilities through the virtual clock's flexible adjustments.
3Measurement precision
If time-difference measurements are made for multiple frames, then clock-rate correction accuracy is improved, but blockout period increases reducing synchronization efficiency
Solution Approach 1:
By segmenting clock adjustments into virtual and hardware components, the patent enables continuous measurement and correction operations. The virtual clock can process measurements and apply corrections without blocking the hardware clock, thereby reducing the effective blockout period while maintaining correction accuracy.
Solution Approach 2:
The patent enables continuous clock synchronization by allowing virtual and hardware clocks to operate simultaneously. The useful action of clock correction continues without interruption as both clocks can be adjusted concurrently, eliminating the need to stop measurements for blockout periods.
Data Source
AI summary
In one embodiment, a method is performed at a node. The method comprises outputting, from a rate-changeable clock included at the node, a first clock signal having a clock rate. The method further comprises generating a second clock signal from the first clock signal for use in determining when transmissions in a network are to start. The method further comprises sending and receiving data from the node using the first clock signal as a line encoding/decoding clock. The method further comprises making relative clock-rate measurements at the node based on transmissions received at the node and using the relative clock-rate measurements to adjust the clock rate of the rate-changeable clock. The method further comprises making clock-state adjustments to the second clock signal.