Rate Limiting Shared Work Queues via MMU Thresholds

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Solution Overview

Problem

In multi-tenant computing environments, concurrent software processes competing for shared hardware resources can lead to unfair access, diminished performance, and security risks due to resource competition and potential denial-of-service (DOS) attacks.

Innovation Solution

Extending translation lookaside buffer (TLB) entries with metrics to limit the rate at which processes submit work to shared work queues, using Deferrable Memory Writes (DMWr) instructions like ENQCMD, and implementing policies such as thresholds and time intervals to abort instructions and trigger MMU faults when capacity is exceeded.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple processes submit requests to the same queue concurrently without rate limiting, then the device can process more work in parallel, but one process may consume all resources to the exclusion of other processes, leading to unfair access and potential denial-of-service attacks

Engineering Contradiction:
Improvework submission rateVSAvoidfair access
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent introduces rate limiting commands as an intermediary mechanism between processes and the shared work queue. These commands act as mediators that regulate and control the flow of work submissions, ensuring that no single process can monopolize the queue while maintaining high overall throughput. The rate limiting layer sits between the submitting processes and the queue, distributing access fairly among multiple processes.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent dynamically adjusts rate limiting parameters such as thresholds and time intervals based on system conditions and process behavior. By changing these parameters adaptively, the system can optimize between allowing high work submission rates for productivity and enforcing fair access through rate limits, resolving the contradiction between these two competing requirements.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If rate limiting is implemented to ensure fair access, then resource consumption is balanced across processes, but the complexity of the system increases due to additional control mechanisms

Engineering Contradiction:
Improvefair accessVSAvoidcontrol mechanism complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The rate limiting mechanism is designed to be self-regulating, using predefined thresholds and time intervals that automatically control work submission rates without requiring complex external management. The system monitors its own state and adjusts accordingly, reducing the need for additional complex control infrastructure while maintaining fair access.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The patent implements rate limiting based on periodic time intervals and threshold checks, creating a rhythmic, predictable control pattern. This periodic approach simplifies the control logic compared to continuous complex monitoring, as it uses regular intervals to assess and regulate work submissions, making the system easier to manage and understand.

Inventive Principle:
Principle #19Periodic action

3Reliability

If rate limiting with thresholds and time intervals is enforced, then DOS attacks are mitigated and fair access is ensured, but the processing time for work submissions increases due to additional checks

Engineering Contradiction:
ImprovesecurityVSAvoidsubmission processing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent pre-configures rate limiting thresholds and time intervals before work submission occurs. By establishing these parameters in advance, the system can quickly evaluate whether a submission should be rate-limited without performing complex real-time analysis, reducing the time penalty for security checks while maintaining DOS mitigation capabilities.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20230004503A1Rate limiting commands for shared work queues
Publication Date: 2023.01.05 INTEL CORP
  • US20230004503A1 patent drawing
  • US20230004503A1 patent drawing
  • US20230004503A1 patent drawing

AI summary

A memory management unit of a processor may receive a command associated with a process. The command may specify an operation to be performed by another device. The memory management unit may determine a counter value associated with a shared work queue of the another device, an indication the shared work queue to be specified by the command. The memory management unit may determine whether to accept or reject the command based on the counter value and a threshold for the process.