Rate Matching Buffering for LTE Parallel Processing

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Solution Overview

Problem

Current rate matching methods in 3GPP LTE systems lack detailed implementation procedures, leading to inefficient resource utilization and increased delays due to complex buffering processes.

Innovation Solution

A specific rate matching method and apparatus that inserts dummy data into bit streams to form even-numbered and odd-numbered rows, buffers them separately, and then rearranges them into a matrix, allowing for efficient interleaving and deletion of dummy data to achieve the required output length, utilizing a two-level storage and ping-pong buffering approach.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If dummy data is inserted and two-level buffering is used for rate matching, then parallel processing efficiency is improved, but device complexity increases

Engineering Contradiction:
Improveparallel processing efficiencyVSAvoidbuffering structure complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The buffering process is segmented into two levels: a first buffer for initial data storage and a second buffer for interleaving operations. This segmentation allows parallel processing of different data portions simultaneously while maintaining organized data flow and reducing overall system complexity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Dummy data is introduced as an intermediary element to facilitate the buffering and interleaving process. The dummy data acts as a placeholder that enables proper data alignment and parallel processing without affecting the actual information content, thereby improving efficiency without requiring complex reorganization logic.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If complex buffering processes are used for rate matching, then data processing completeness is improved, but delay increases

Engineering Contradiction:
Improvedata processing completenessVSAvoidprocessing delay
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

Data is pre-organized into even and odd rows before the interleaving operation. This preliminary arrangement ensures that all necessary data is properly positioned in advance, allowing the subsequent interleaving and pruning operations to proceed efficiently without requiring additional processing steps or causing delays.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The pruning operation selectively skips over dummy data elements during the output phase, rapidly extracting only the valid data portions. This skipping mechanism allows the system to quickly pass through unnecessary data elements and deliver the required output without being bottlenecked by the presence of dummy fillers.

Inventive Principle:
Principle #21Skipping (Rushing through)

Data Source

PatentUS8718212B2Rate matching method and apparatus
Publication Date: 2014.05.06 HONOR DEVICE CO LTD
  • US8718212B2 patent drawing
  • US8718212B2 patent drawing
  • US8718212B2 patent drawing

AI summary

Embodiments of the present invention provide a rate matching method and apparatus. The method includes: receiving bit data of a first, a second, and a third input subblock, inserting dummy data into bit data in each subblock to respectively form even-numbered rows and odd-numbered rows of a matrix to be buffered for each subblock; inputting bit data of the even-numbered rows in the even-numbered row buffer and bit data of the odd-numbered rows in the odd-numbered row buffer of each subblock to a second buffer, and forming a matrix by using the bit data of the even-numbered rows and the bit data of the odd-numbered rows; controlling the second buffer to send data at the specified address; selecting data sent by the second buffer; and deleting the dummy data from the selected data to obtain valid output data.