Rate Matching via Pre-calculated Padding Bit Positions
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Solution Overview
Problem
Existing rate matching techniques in LTE systems introduce latency and require significant memory usage, which need to be minimized for efficient data transmission.
Innovation Solution
A method and apparatus that determine and store bit positions of interleaver padding bits at the beginning of a transmission time interval, allowing for efficient matching of output bits from a channel encoding stage to a physical transmission channel by reusing stored padding bit positions, and performing bit pruning to adapt the data rate, which includes pre-calculating dummy and filler bit positions in a virtual circular buffer and discarding unnecessary bits to match the physical channel's capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If rate matching is implemented using traditional methods with full buffering and sequential processing, then accurate rate matching is achieved, but latency increases and memory usage increases
Solution Approach 1:
The patent pre-calculates and stores the positions of padding bits in a lookup table before the actual rate matching operation. This preliminary action allows the rate matching process to directly access pre-determined positions without performing complex calculations during real-time operation, thereby reducing latency while maintaining accurate rate matching through the use of pre-computed position data
Solution Approach 2:
The patent segments the rate matching process into distinct operations: channel encoding, parallel bit position determination using pre-stored lookup tables, and selective buffering. By dividing the process into independent parallel segments, the system achieves accurate rate matching without requiring sequential processing of the entire bit stream, thus reducing latency
2Reliability
If rate matching uses extensive buffering and sequential bit position determination, then complete bit stream processing is ensured, but memory usage increases
Solution Approach 1:
The patent pre-calculates padding bit positions and stores them in a compact lookup table format. This preliminary computation reduces the memory requirements during actual rate matching operations, as the system only needs to store position indices rather than complete bit streams in buffer memory, thus maintaining bit stream completeness with reduced memory usage
Solution Approach 2:
The patent uses a virtual circular buffer model that copies only the necessary position information from the channel encoder output rather than maintaining extensive physical buffers. The virtual buffer concept allows complete bit stream processing to be simulated with minimal actual memory storage by using mathematical indexing and modular arithmetic
3Measurement precision
If bit position determination is performed sequentially after channel encoding, then processing accuracy is maintained, but processing speed decreases
Solution Approach 1:
The patent pre-computes and stores the mapping between channel encoder output positions and rate matcher input positions in lookup tables. This preliminary action enables bit position determination to be performed by simple table lookups rather than sequential calculation, maintaining positional accuracy through pre-validated mappings while dramatically increasing processing speed through parallel access
Solution Approach 2:
The patent segments the bit position determination into independent parallel operations that can be executed simultaneously using the pre-stored lookup tables. Each code block's bit positions can be determined in parallel without sequential dependencies, maintaining accuracy through the use of pre-computed position data while achieving high processing throughput
Data Source
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AI summary
A technique for rate matching a bit stream (c(0-2)(k)) output from a channel encoder (102) to a data transmission rate on a physical transmission channel is described. A method embodiment of the technique comprises the steps of determining, at a beginning of a transmission time interval for a transmission of one or more code blocks on the transmission channel, bit positions of interleaver padding bits (dummy and/or filler bits) in an output buffer for buffering the output bits before transmission on the physical transmission channel; storing the determined padding bit positions (114); and determining, based on the stored padding bit positions, positions (d(0-2)(k)) of the output bits from the channel encoding stage (102) in the output buffer, wherein the stored padding bit positions are re-used for each of the one or more code blocks.