Rate-Matching for Uplink Transport Block Processing Over Multiple Slots

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Solution Overview

Problem

The next-generation wireless communication system, 5G NR, faces challenges in maintaining adequate uplink coverage due to higher carrier frequencies, leading to increased path loss, particularly in cellular systems, where low transmit power at the user equipment (UE) side acts as a bottleneck.

Innovation Solution

Implementing rate-matching mechanisms for transport block processing over multiple slots, including bit interleaving and bit selection strategies, to improve link budget and coverage by optimizing resource allocation and bit distribution across slots.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If higher carrier frequencies are used in 5G NR, then data rate and spectral efficiency are improved, but path loss increases and uplink coverage deteriorates

Engineering Contradiction:
Improvedata rateVSAvoidpath loss
Core Design Contradiction:
ProductivityVSObject-affected harmful factors

Solution Approach 1:

The transport block is divided into multiple code blocks, which are further segmented into code block groups. This segmentation allows flexible distribution of data across multiple slots, enabling the system to maintain high data rates while managing path loss effects through distributed transmission.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces time domain extension by processing transport blocks over multiple slots rather than a single slot. This adds a temporal dimension to the transmission, allowing the system to compensate for path loss through repeated transmissions across different time periods while maintaining high spectral efficiency.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Power

If low transmit power is used at UE side, then device complexity and power consumption are reduced, but uplink coverage is insufficient

Engineering Contradiction:
Improvetransmit powerVSAvoiduplink coverage
Core Design Contradiction:
PowerVSReliability

Solution Approach 1:

The patent implements continuous transmission of code block groups across multiple slots, ensuring that the useful action of data transmission continues without interruption. This continuous action over time compensates for the low transmit power by distributing the transmission energy across multiple time periods, maintaining reliable uplink coverage.

Inventive Principle:
Principle #20Continuity of useful action

Solution Approach 2:

The system performs preliminary processing of the transport block into code blocks and code block groups before transmission. This preliminary action allows for optimized bit interleaving and rate matching that can be applied across multiple slots, ensuring that the low transmit power is efficiently utilized to maintain reliable coverage.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If transport block is processed over multiple slots, then link budget and coverage are improved, but device complexity and processing time increase

Engineering Contradiction:
ImprovecoverageVSAvoidprocessing complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

By segmenting the transport block into code blocks and code block groups, the patent reduces the processing complexity of each individual slot while maintaining the benefits of multi-slot transmission. Each segment can be processed independently, making the overall complex multi-slot processing more manageable.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces dynamic adaptability in the multi-slot processing through configurable parameters such as the number of code block groups and their distribution across slots. This dynamic approach allows the system to adjust the processing complexity based on actual transmission conditions, balancing coverage improvement with device complexity.

Inventive Principle:
Principle #15Dynamics

4Productivity

If bit interleaving is applied across multiple slots, then bit distribution and resource allocation are optimized, but processing time and computational overhead increase

Engineering Contradiction:
Improveresource allocation efficiencyVSAvoidprocessing time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The bit interleaving process is segmented into operations performed on code block groups rather than individual bits across all slots. This segmentation reduces the computational overhead by processing larger units of data together, optimizing resource allocation efficiency while managing processing time.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary bit interleaving and rate matching calculations before the actual transmission across multiple slots. This preliminary action optimizes the bit distribution and resource allocation in advance, reducing the processing time required during transmission while maintaining high resource allocation efficiency.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20240224268A1Rate-matching for transport block processing over multiple slots for physical uplink shared channel
Publication Date: 2024.07.04 INTEL CORP
  • US20240224268A1 patent drawing
  • US20240224268A1 patent drawing
  • US20240224268A1 patent drawing

AI summary

Various embodiments herein provide techniques for uplink transport block transmission over multiple slots, e.g. using bit interleaving and/or rate matching. Other embodiments may be described and claimed.