Ratioless Write Port SRAM Cell for Boolean Operations

Solution Overview

Problem

Existing SRAM cells require a strong write transistor ratio relative to the storage transistor to perform Boolean operations like XOR and XNOR, leading to inefficiencies and increased complexity due to the need for stronger transistors, which complicates the manufacturing process and increases costs.

Innovation Solution

A dual port SRAM cell and processing array design that incorporates a ratioless write port, allowing for efficient performance of Boolean operations such as AND, OR, NAND, NOR, XOR, and XNOR without the need for stronger write transistors, achieved through a modified circuit configuration that enables selective writing without overpowering the storage latch.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If stronger write transistors are used to perform Boolean operations in SRAM cells, then the writing capability is improved, but the device complexity and manufacturing cost increase

Engineering Contradiction:

Improvewriting capabilityVSAvoidtransistor strength ratio

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent inverts the traditional approach by making the storage transistors stronger than the write transistors (write-to-storage ratio of 1:2 or 1:3), opposite to the conventional requirement of 2:3 or higher. This inversion is achieved through specific transistor sizing where storage transistors M1 and M2 have width-to-length ratios of 1.0-1.5, while write transistors M3-M6 have ratios of 0.5-0.75, allowing successful writing despite weaker write transistors

Inventive Principle:

Principle #13The other way round (Inversion)

Solution Approach 2:

The patent changes the critical parameter of transistor strength ratio from the conventional write-dominant design to a storage-dominant design. By adjusting the width-to-length ratios of transistors and modifying the circuit configuration with cross-coupled NMOS and PMOS transistors, the system achieves writing capability with a write-to-storage ratio of 1:2 or 1:3, fundamentally changing the parameter landscape

Inventive Principle:

Principle #35Parameter changes

2Reliability

If stronger write transistors are used to overwrite storage data, then the write operation reliability is improved, but the manufacturing cost increases

Engineering Contradiction:

Improvewrite operation reliabilityVSAvoidmanufacturing cost

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The patent inverts the traditional approach by making the storage transistors stronger than the write transistors (write-to-storage ratio of 1:2 or 1:3), opposite to the conventional requirement of 2:3 or higher. This inversion is achieved through specific transistor sizing where storage transistors M1 and M2 have width-to-length ratios of 1.0-1.5, while write transistors M3-M6 have ratios of 0.5-0.75, allowing successful writing despite weaker write transistors

Inventive Principle:

Principle #13The other way round (Inversion)

Solution Approach 2:

The patent changes the critical parameter of transistor strength ratio from the conventional write-dominant design to a storage-dominant design. By adjusting the width-to-length ratios of transistors and modifying the circuit configuration with cross-coupled NMOS and PMOS transistors, the system achieves writing capability with a write-to-storage ratio of 1:2 or 1:3, fundamentally changing the parameter landscape

Inventive Principle:

Principle #35Parameter changes

3Productivity

If a higher write ratio is used to ensure successful writing, then the writing performance is improved, but the transistor size and circuit complexity increase

Engineering Contradiction:

Improvewriting performanceVSAvoidtransistor size

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent inverts the traditional approach by making the storage transistors stronger than the write transistors (write-to-storage ratio of 1:2 or 1:3), opposite to the conventional requirement of 2:3 or higher. This inversion is achieved through specific transistor sizing where storage transistors M1 and M2 have width-to-length ratios of 1.0-1.5, while write transistors M3-M6 have ratios of 0.5-0.75, allowing successful writing despite weaker write transistors

Inventive Principle:

Principle #13The other way round (Inversion)

Solution Approach 2:

The patent changes the critical parameter of transistor strength ratio from the conventional write-dominant design to a storage-dominant design. By adjusting the width-to-length ratios of transistors and modifying the circuit configuration with cross-coupled NMOS and PMOS transistors, the system achieves writing capability with a write-to-storage ratio of 1:2 or 1:3, fundamentally changing the parameter landscape

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS10854284B1Computational memory cell and processing array device with ratioless write port

Publication Date: 2020.12.01 GSI TECHNOLOGY INC

AI summary

A computational memory cell and processing array have a ratioless write port so that a write to the memory cell does not need to overcome the drive strength of a PMOS transistor that is part of the storage cell of the memory cell. The computational memory cell also may have a second read port that has an isolation circuit.