Rational Clock Divider for Balanced Phase-Aligned Output Clocks
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Solution Overview
Problem
Existing clock generators, such as voltage controlled oscillators and phase lock loops, often produce unbalanced digital clock signals due to unequal rise and fall times, leading to pattern noise and inter-symbol interference, and require complex analog circuit designs to generate balanced clocks with limited output frequencies.
Innovation Solution
A method and system for dividing an input clock by an integer or non-integer divisor to generate balanced, phase-aligned clocks with a 50% duty cycle, using a device that includes a measurement unit to determine the input clock period, a secondary clock synthesizer, a shift actuator, and a balancer to adjust delays and combine signals, allowing for flexible generation of balanced or unbalanced divided clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If complex analog circuit design is used to generate balanced clocks, then balanced clock generation is achieved, but device complexity increases and output frequency selection is limited
Solution Approach 1:
The patent replaces complex analog circuit design with a digital domain implementation using delay elements and logic gates. The clock balancing function is achieved through digital signal processing rather than analog components, significantly reducing device complexity while maintaining the ability to generate balanced clocks with 50% duty cycle.
Solution Approach 2:
The digital domain implementation provides a universal solution that can generate multiple output frequencies by simply changing the division ratio parameters. The same circuit architecture can produce different balanced clock frequencies (e.g., 50MHz, 100MHz, 200MHz) without requiring separate analog circuit designs, thus enabling flexible frequency selection.
2Reliability
If integer division by power of two is used, then balanced clocks are generated, but output frequency selection is limited
Solution Approach 1:
The patent implements dynamic and flexible frequency division by allowing programmable division ratios. The circuit can perform integer division by any integer N, not just powers of two. This is achieved through configurable delay elements and logic gates that can be programmed to divide the input clock frequency by any integer value, enabling output frequencies such as 50MHz, 100MHz, 200MHz from a 500MHz input clock.
3Reliability
If delay is increased to align phases, then phase alignment is improved, but signal delay increases
Solution Approach 1:
The patent applies local quality by using different delay values for different signal paths within the circuit. The delay elements are configured to provide precise local adjustments to align the phases of intermediate signals. By optimizing the delay in each specific path rather than adding uniform delay throughout, the circuit achieves phase alignment while minimizing the total signal delay from input to output.
Data Source
AI summary
This disclosure can provide methods, apparatus, and systems for dividing an input clock or master clock by an integer or non-integer divisor and generating one or more balanced, i.e., 50% duty cycle, divided that are phase-aligned to the input clock. The non-integer divisors can include half-integers, N/2, e.g. the division can be denoted 2:N. The value of N for each phase-aligned, balanced, divided clock can be distinct. The method can include generating an input clock signal having an input clock frequency, generating a secondary clock signal that transitions between a first state and a second state based on the input clock signal, generating a delayed secondary clock signal that is time delayed relative to the secondary clock signal, and generating the output clock signal that has a frequency that is a non-integer division of the input clock frequency.