Rational Frequency Divider Circuit for Multi-Phase Clock Generation
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Solution Overview
Problem
Integrated circuits, such as field programmable gate arrays (FPGAs), require multiple clock signal phases that traditional phase-locked loops (PLLs) cannot efficiently generate, leading to increased die area and slow response times.
Innovation Solution
A frequency divider circuit comprising an adder circuit, multiplexer circuits, and a phase interpolator circuit that generates a frequency divided signal by dividing the input clock signals by a rational number, allowing for adjustable phase and frequency adjustments without the need for multiple PLLs, thus reducing die area and improving response speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional phase-locked loops (PLLs) are used to generate multiple clock signal phases, then frequency division and phase adjustment can be achieved, but the die area increases and response time becomes slow
Solution Approach 1:
The patent divides the frequency division function into multiple independent frequency divider circuits, each handling a specific division ratio. This segmentation allows each circuit to be optimized independently and reduces the area required compared to a single large PLL system. The adder circuit is also segmented into multiple adders that process different bits of the division ratio separately.
Solution Approach 2:
The frequency divider circuit is designed to be universal by accepting any rational number division ratio (N/M) and generating multiple clock phases simultaneously. The same basic circuit structure can be configured for different division ratios by changing the control signals to the multiplexers and the values in the adders, eliminating the need for multiple dedicated PLL circuits for different phases.
2Adaptability or versatility
If traditional phase-locked loops (PLLs) are used to generate multiple clock signal phases, then frequency division can be achieved, but the response time becomes slow
Solution Approach 1:
The frequency divider circuit employs dynamic control through the adder circuit that continuously calculates the phase difference between input and output clocks and adjusts the output phase in real-time. The multiplexers dynamically select between different input clocks based on the calculated phase relationship, enabling fast response to frequency and phase changes without the slow feedback loop of traditional PLLs.
3Adaptability or versatility
If multiple PLLs are used to generate multiple clock signal phases, then adequate phase coverage can be achieved, but the die area increases significantly
Solution Approach 1:
The patent merges multiple frequency division functions into a single integrated circuit that can simultaneously generate multiple clock phases. The adder circuit combines the division ratio information and phase difference calculations in one unit, and the multiplexers combine multiple input clock signals to produce the required output phases, replacing what would traditionally require multiple separate PLL circuits.
4Area of stationary object
If frequency divider circuits with rational number division are used, then multiple clock phases can be generated with reduced die area, but circuit complexity increases
Solution Approach 1:
The patent handles the complexity of rational number division (N/M) by parameterizing the circuit behavior through control signals. The adder circuit takes the division ratio parameters N and M as inputs and dynamically adjusts its operation accordingly. The multiplexers are controlled by signals derived from these parameters, allowing the same hardware structure to adapt to different division ratios without increasing physical complexity.
Data Source
AI summary
A frequency divider circuit includes an adder circuit, multiplexer circuits, and a phase interpolator circuit. The adder circuit generates a summed value. The multiplexer circuits receive first periodic signals and generate second periodic signals by selecting among the first periodic signals based on the summed value. The phase interpolator circuit generates a third periodic signal using a weighted average of the second periodic signals that is determined based on the summed value.