Fixed Logic Circuit for Multiplication by Rational with Selectable Rounding
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Solution Overview
Problem
Existing integrated circuit designs face challenges in efficiently implementing division operations, particularly when the divisor is a constant, as they require complex logic and significant resources, and truncating binary expansion arrays for multiplication by a constant rational leads to accuracy issues and high silicon area usage.
Innovation Solution
A fixed logic circuit using a truncated summation array with corrective constants for directed rounding modes, configured to perform binary multiplication by a constant rational, reduces resource usage and achieves accurate results through selective truncation and correction logic.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a truncated summation array is used for multiplication by a constant rational, then the silicon area and power consumption are reduced, but the calculation accuracy deteriorates due to truncation errors
Solution Approach 1:
The patent extracts and removes the problematic infinite tail of the CSD expansion from the summation array, retaining only the finite most significant bits. This truncation reduces silicon area while the extracted portion is handled separately through corrective constants that compensate for the truncation error and restore calculation accuracy.
Solution Approach 2:
The patent changes the parameter of the summation array from an infinite sequence to a finite sequence by selecting a truncation point. This parameter change reduces the hardware resources required while corrective constants are introduced to maintain the desired precision by compensating for the removed terms.
2Measurement precision
If the infinite CSD expansion is fully implemented, then the calculation accuracy is maintained, but the silicon area and device complexity increase significantly
Solution Approach 1:
The patent separates the infinite CSD expansion into two parts: the finite most significant bits that are implemented in the summation array, and the infinite least significant bits that are represented by corrective constants. This extraction allows accurate calculation without implementing the entire infinite expansion in hardware.
Solution Approach 2:
The patent performs preliminary analysis to identify the truncation point where the remaining terms can be adequately represented by corrective constants. This preliminary action determines the optimal balance between summation array size and corrective constant precision, reducing silicon area while maintaining accuracy.
3Reliability
If faithful rounding is used to handle truncation errors, then the error tolerance is acceptable, but the device complexity increases due to additional rounding logic
Solution Approach 1:
The patent merges the rounding functionality into the corrective constants themselves. Instead of implementing separate rounding logic, the corrective constants are designed to inherently provide the desired rounding behavior (directed rounding or round-to-nearest), combining error compensation and rounding into a single mechanism that reduces device complexity.
Solution Approach 2:
The corrective constants serve multiple functions: they compensate for truncation errors, provide the necessary precision, and implement the desired rounding mode. This multi-functionality eliminates the need for separate rounding logic while maintaining reliability and acceptable error tolerance.
4Adaptability or versatility
If different rounding modes are supported, then the adaptability and versatility are improved, but the device complexity increases due to multiple corrective constants and selection logic
Solution Approach 1:
The patent implements dynamic selection of corrective constants based on the desired rounding mode. Instead of hardwiring different rounding modes, the system dynamically selects the appropriate corrective constant from a set of pre-computed values, allowing adaptability while keeping the selection logic simple through efficient encoding and selection mechanisms.
Solution Approach 2:
The patent changes the parameter of the corrective constants to represent different rounding modes. By pre-computing and storing multiple corrective constants corresponding to different rounding modes (directed rounding, round-to-nearest with various tie-breaking rules), the system achieves versatility while the actual selection involves simple parameter switching rather than complex logic.
Data Source
AI summary
A fixed logic circuit for performing multiplication of an input x by a constant rational p/q so as to calculate an output y according to a directed rounding or round-to-nearest rounding mode. Fixed logic hardware is derived comprising an addition array configured to operate on canonical signed digit (CSD) forms of binary values (a CSD array) so as to form an approximation of a multiplication of an input x [m−1:0] by a rational p/q. A truncated summation array of a finite sequence of most significant bits of an infinite CSD expansion of the rational p/q operating on the bits of the input x satisfiesΔhigh-Δlow<1q.Registers define a plurality of corrective constants for a respective plurality of rounding modes, and selection logic selects the respective corrective constant for that rounding mode in dependence on a rounding mode in which the truncated summation array is to operate.